sim_object.hh revision 11067
1451SN/A/* 22212SN/A * Copyright (c) 2015 ARM Limited 3451SN/A * All rights reserved 4451SN/A * 5451SN/A * The license below extends only to copyright in the software and shall 6451SN/A * not be construed as granting a license to any other intellectual 7451SN/A * property including but not limited to intellectual property relating 8451SN/A * to a hardware implementation of the functionality of the software 9451SN/A * licensed hereunder. You may use the software subject to the license 10451SN/A * terms below provided that you ensure that this notice is replicated 11451SN/A * unmodified and in its entirety in all distributions of the software, 12451SN/A * modified or unmodified, in source code or in binary form. 13451SN/A * 14451SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 15451SN/A * Copyright (c) 2010 Advanced Micro Devices, Inc. 16451SN/A * All rights reserved. 17451SN/A * 18451SN/A * Redistribution and use in source and binary forms, with or without 19451SN/A * modification, are permitted provided that the following conditions are 20451SN/A * met: redistributions of source code must retain the above copyright 21451SN/A * notice, this list of conditions and the following disclaimer; 22451SN/A * redistributions in binary form must reproduce the above copyright 23451SN/A * notice, this list of conditions and the following disclaimer in the 24451SN/A * documentation and/or other materials provided with the distribution; 25451SN/A * neither the name of the copyright holders nor the names of its 26451SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31451SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32451SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35451SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362680Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371070SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381070SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391070SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402212SN/A * 413565Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 422212SN/A * Nathan Binkert 432212SN/A */ 444762Snate@binkert.org 452212SN/A/* @file 46885SN/A * User Console Definitions 472343SN/A */ 48885SN/A 49885SN/A#ifndef __SIM_OBJECT_HH__ 50885SN/A#define __SIM_OBJECT_HH__ 512212SN/A 52451SN/A#include <iostream> 53451SN/A#include <list> 545569Snate@binkert.org#include <map> 551885SN/A#include <string> 561885SN/A#include <vector> 571885SN/A 582680Sktlim@umich.edu#include "enums/MemoryMode.hh" 591885SN/A#include "params/SimObject.hh" 601885SN/A#include "sim/drain.hh" 615569Snate@binkert.org#include "sim/eventq_impl.hh" 621885SN/A#include "sim/serialize.hh" 631885SN/A 641885SN/Aclass BaseCPU; 652680Sktlim@umich.educlass Event; 661885SN/Aclass ProbeManager; 671885SN/A/** 681855SN/A * Abstract superclass for simulation objects. Represents things that 691855SN/A * correspond to physical components and can be specified via the 701855SN/A * config file (CPUs, caches, etc.). 711855SN/A * 721855SN/A * SimObject initialization is controlled by the instantiate method in 731855SN/A * src/python/m5/simulate.py. There are slightly different 741855SN/A * initialization paths when starting the simulation afresh and when 751855SN/A * loading from a checkpoint. After instantiation and connecting 761855SN/A * ports, simulate.py initializes the object using the following call 771855SN/A * sequence: 781855SN/A * 791855SN/A * <ol> 801855SN/A * <li>SimObject::init() 811855SN/A * <li>SimObject::regStats() 821855SN/A * <li><ul> 831855SN/A * <li>SimObject::initState() if starting afresh. 841855SN/A * <li>SimObject::loadState() if restoring from a checkpoint. 851855SN/A * </ul> 861855SN/A * <li>SimObject::resetStats() 871855SN/A * <li>SimObject::startup() 881492SN/A * <li>Drainable::drainResume() if resuming from a checkpoint. 89887SN/A * </ol> 90451SN/A * 911492SN/A * @note Whenever a method is called on all objects in the simulator's 921492SN/A * object tree (e.g., init(), startup(), or loadState()), a pre-order 931492SN/A * depth-first traversal is performed (see descendants() in 941070SN/A * SimObject.py). This has the effect of calling the method on the 95887SN/A * parent node <i>before</i> its children. 961070SN/A */ 971070SN/Aclass SimObject : public EventManager, public Serializable, public Drainable 981070SN/A{ 99887SN/A private: 100885SN/A typedef std::vector<SimObject *> SimObjectList; 101887SN/A 102887SN/A /** List of all instantiated simulation objects. */ 103885SN/A static SimObjectList simObjectList; 104887SN/A 1051070SN/A /** Manager coordinates hooking up probe points with listeners. */ 1061070SN/A ProbeManager *probeManager; 1071070SN/A 1081070SN/A protected: 1095991Ssteve.reinhardt@amd.com /** Cached copy of the object parameters. */ 1101039SN/A const SimObjectParams *_params; 1111070SN/A 1121070SN/A public: 113887SN/A typedef SimObjectParams Params; 114887SN/A const Params *params() const { return _params; } 1151885SN/A SimObject(const Params *_params); 116841SN/A virtual ~SimObject(); 1171082SN/A 1181082SN/A public: 1191082SN/A 1201082SN/A virtual const std::string name() const { return params()->name; } 1211067SN/A 1221067SN/A /** 1231070SN/A * init() is called after all C++ SimObjects have been created and 1241070SN/A * all ports are connected. Initializations that are independent 125451SN/A * of unserialization but rely on a fully instantiated and 126451SN/A * connected SimObject graph should be done here. 1274762Snate@binkert.org */ 1282212SN/A virtual void init(); 1292212SN/A 130451SN/A /** 1312680Sktlim@umich.edu * loadState() is called on each SimObject when restoring from a 132451SN/A * checkpoint. The default implementation simply calls 133451SN/A * unserialize() if there is a corresponding section in the 1342212SN/A * checkpoint. However, objects can override loadState() to get 135 * other behaviors, e.g., doing other programmed initializations 136 * after unserialize(), or complaining if no checkpoint section is 137 * found. 138 * 139 * @param cp Checkpoint to restore the state from. 140 */ 141 virtual void loadState(CheckpointIn &cp); 142 143 /** 144 * initState() is called on each SimObject when *not* restoring 145 * from a checkpoint. This provides a hook for state 146 * initializations that are only required for a "cold start". 147 */ 148 virtual void initState(); 149 150 /** 151 * Register statistics for this object. 152 */ 153 virtual void regStats(); 154 155 /** 156 * Reset statistics associated with this object. 157 */ 158 virtual void resetStats(); 159 160 /** 161 * Register probe points for this object. 162 */ 163 virtual void regProbePoints(); 164 165 /** 166 * Register probe listeners for this object. 167 */ 168 virtual void regProbeListeners(); 169 170 /** 171 * Get the probe manager for this object. 172 */ 173 ProbeManager *getProbeManager(); 174 175 /** 176 * startup() is the final initialization call before simulation. 177 * All state is initialized (including unserialized state, if any, 178 * such as the curTick() value), so this is the appropriate place to 179 * schedule initial event(s) for objects that need them. 180 */ 181 virtual void startup(); 182 183 /** 184 * Provide a default implementation of the drain interface for 185 * objects that don't need draining. 186 */ 187 DrainState drain() M5_ATTR_OVERRIDE { return DrainState::Drained; } 188 189 /** 190 * Write back dirty buffers to memory using functional writes. 191 * 192 * After returning, an object implementing this method should have 193 * written all its dirty data back to memory. This method is 194 * typically used to prepare a system with caches for 195 * checkpointing. 196 */ 197 virtual void memWriteback() {}; 198 199 /** 200 * Invalidate the contents of memory buffers. 201 * 202 * When the switching to hardware virtualized CPU models, we need 203 * to make sure that we don't have any cached state in the system 204 * that might become stale when we return. This method is used to 205 * flush all such state back to main memory. 206 * 207 * @warn This does <i>not</i> cause any dirty state to be written 208 * back to memory. 209 */ 210 virtual void memInvalidate() {}; 211 212 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE {}; 213 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE {}; 214 215 /** 216 * Serialize all SimObjects in the system. 217 */ 218 static void serializeAll(CheckpointOut &cp); 219 220#ifdef DEBUG 221 public: 222 bool doDebugBreak; 223 static void debugObjectBreak(const std::string &objs); 224#endif 225 226 /** 227 * Find the SimObject with the given name and return a pointer to 228 * it. Primarily used for interactive debugging. Argument is 229 * char* rather than std::string to make it callable from gdb. 230 */ 231 static SimObject *find(const char *name); 232}; 233 234/** 235 * Base class to wrap object resolving functionality. 236 * 237 * This can be provided to the serialization framework to allow it to 238 * map object names onto C++ objects. 239 */ 240class SimObjectResolver 241{ 242 public: 243 virtual ~SimObjectResolver() { } 244 245 // Find a SimObject given a full path name 246 virtual SimObject *resolveSimObject(const std::string &name) = 0; 247}; 248 249#ifdef DEBUG 250void debugObjectBreak(const char *objs); 251#endif 252 253#endif // __SIM_OBJECT_HH__ 254