sim_object.hh revision 10911
12SN/A/* 210911Sandreas.sandberg@arm.com * Copyright (c) 2015 ARM Limited 310911Sandreas.sandberg@arm.com * All rights reserved 410911Sandreas.sandberg@arm.com * 510911Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 610911Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 710911Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 810911Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 910911Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1010911Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1110911Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1210911Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1310911Sandreas.sandberg@arm.com * 141762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 157534Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 432SN/A */ 442SN/A 452SN/A/* @file 462SN/A * User Console Definitions 472SN/A */ 482SN/A 492SN/A#ifndef __SIM_OBJECT_HH__ 502SN/A#define __SIM_OBJECT_HH__ 512SN/A 525491Sgblack@eecs.umich.edu#include <iostream> 535491Sgblack@eecs.umich.edu#include <list> 542SN/A#include <map> 555491Sgblack@eecs.umich.edu#include <string> 562SN/A#include <vector> 572SN/A 588737Skoansin.tan@gmail.com#include "enums/MemoryMode.hh" 594762Snate@binkert.org#include "params/SimObject.hh" 609342SAndreas.Sandberg@arm.com#include "sim/drain.hh" 619356Snilay@cs.wisc.edu#include "sim/eventq_impl.hh" 6256SN/A#include "sim/serialize.hh" 632SN/A 642797Sktlim@umich.educlass BaseCPU; 652797Sktlim@umich.educlass Event; 6610023Smatt.horsnell@ARM.comclass ProbeManager; 679196SAndreas.Sandberg@arm.com/** 682SN/A * Abstract superclass for simulation objects. Represents things that 692SN/A * correspond to physical components and can be specified via the 702SN/A * config file (CPUs, caches, etc.). 719196SAndreas.Sandberg@arm.com * 729196SAndreas.Sandberg@arm.com * SimObject initialization is controlled by the instantiate method in 739196SAndreas.Sandberg@arm.com * src/python/m5/simulate.py. There are slightly different 749196SAndreas.Sandberg@arm.com * initialization paths when starting the simulation afresh and when 759196SAndreas.Sandberg@arm.com * loading from a checkpoint. After instantiation and connecting 769196SAndreas.Sandberg@arm.com * ports, simulate.py initializes the object using the following call 779196SAndreas.Sandberg@arm.com * sequence: 789196SAndreas.Sandberg@arm.com * 799196SAndreas.Sandberg@arm.com * <ol> 809196SAndreas.Sandberg@arm.com * <li>SimObject::init() 819196SAndreas.Sandberg@arm.com * <li>SimObject::regStats() 829196SAndreas.Sandberg@arm.com * <li><ul> 839196SAndreas.Sandberg@arm.com * <li>SimObject::initState() if starting afresh. 849196SAndreas.Sandberg@arm.com * <li>SimObject::loadState() if restoring from a checkpoint. 859196SAndreas.Sandberg@arm.com * </ul> 869196SAndreas.Sandberg@arm.com * <li>SimObject::resetStats() 879196SAndreas.Sandberg@arm.com * <li>SimObject::startup() 889342SAndreas.Sandberg@arm.com * <li>Drainable::drainResume() if resuming from a checkpoint. 899196SAndreas.Sandberg@arm.com * </ol> 909196SAndreas.Sandberg@arm.com * 919196SAndreas.Sandberg@arm.com * @note Whenever a method is called on all objects in the simulator's 929196SAndreas.Sandberg@arm.com * object tree (e.g., init(), startup(), or loadState()), a pre-order 939196SAndreas.Sandberg@arm.com * depth-first traversal is performed (see descendants() in 949196SAndreas.Sandberg@arm.com * SimObject.py). This has the effect of calling the method on the 959196SAndreas.Sandberg@arm.com * parent node <i>before</i> its children. 962SN/A */ 979342SAndreas.Sandberg@arm.comclass SimObject : public EventManager, public Serializable, public Drainable 982SN/A{ 992SN/A private: 1002SN/A typedef std::vector<SimObject *> SimObjectList; 1012SN/A 1029196SAndreas.Sandberg@arm.com /** List of all instantiated simulation objects. */ 1032SN/A static SimObjectList simObjectList; 1042SN/A 10510023Smatt.horsnell@ARM.com /** Manager coordinates hooking up probe points with listeners. */ 10610023Smatt.horsnell@ARM.com ProbeManager *probeManager; 10710023Smatt.horsnell@ARM.com 1084762Snate@binkert.org protected: 1099196SAndreas.Sandberg@arm.com /** Cached copy of the object parameters. */ 1104762Snate@binkert.org const SimObjectParams *_params; 1114762Snate@binkert.org 1122SN/A public: 1134762Snate@binkert.org typedef SimObjectParams Params; 1144762Snate@binkert.org const Params *params() const { return _params; } 1154762Snate@binkert.org SimObject(const Params *_params); 11610422Sandreas.hansson@arm.com virtual ~SimObject(); 1172SN/A 1185034Smilesck@eecs.umich.edu public: 1195034Smilesck@eecs.umich.edu 1201553SN/A virtual const std::string name() const { return params()->name; } 121265SN/A 1227532Ssteve.reinhardt@amd.com /** 1237532Ssteve.reinhardt@amd.com * init() is called after all C++ SimObjects have been created and 1247532Ssteve.reinhardt@amd.com * all ports are connected. Initializations that are independent 1257532Ssteve.reinhardt@amd.com * of unserialization but rely on a fully instantiated and 1267532Ssteve.reinhardt@amd.com * connected SimObject graph should be done here. 1277532Ssteve.reinhardt@amd.com */ 128465SN/A virtual void init(); 129465SN/A 1307532Ssteve.reinhardt@amd.com /** 1317532Ssteve.reinhardt@amd.com * loadState() is called on each SimObject when restoring from a 1327532Ssteve.reinhardt@amd.com * checkpoint. The default implementation simply calls 1337532Ssteve.reinhardt@amd.com * unserialize() if there is a corresponding section in the 1347532Ssteve.reinhardt@amd.com * checkpoint. However, objects can override loadState() to get 1357532Ssteve.reinhardt@amd.com * other behaviors, e.g., doing other programmed initializations 1367532Ssteve.reinhardt@amd.com * after unserialize(), or complaining if no checkpoint section is 1377532Ssteve.reinhardt@amd.com * found. 1389196SAndreas.Sandberg@arm.com * 1399196SAndreas.Sandberg@arm.com * @param cp Checkpoint to restore the state from. 1407532Ssteve.reinhardt@amd.com */ 14110905Sandreas.sandberg@arm.com virtual void loadState(CheckpointIn &cp); 1427532Ssteve.reinhardt@amd.com 1437532Ssteve.reinhardt@amd.com /** 1447532Ssteve.reinhardt@amd.com * initState() is called on each SimObject when *not* restoring 1457532Ssteve.reinhardt@amd.com * from a checkpoint. This provides a hook for state 1467532Ssteve.reinhardt@amd.com * initializations that are only required for a "cold start". 1477532Ssteve.reinhardt@amd.com */ 1487532Ssteve.reinhardt@amd.com virtual void initState(); 1497532Ssteve.reinhardt@amd.com 1509196SAndreas.Sandberg@arm.com /** 1519196SAndreas.Sandberg@arm.com * Register statistics for this object. 1529196SAndreas.Sandberg@arm.com */ 1532SN/A virtual void regStats(); 1549196SAndreas.Sandberg@arm.com 1559196SAndreas.Sandberg@arm.com /** 1569196SAndreas.Sandberg@arm.com * Reset statistics associated with this object. 1579196SAndreas.Sandberg@arm.com */ 158330SN/A virtual void resetStats(); 1592SN/A 1607532Ssteve.reinhardt@amd.com /** 16110023Smatt.horsnell@ARM.com * Register probe points for this object. 16210023Smatt.horsnell@ARM.com */ 16310023Smatt.horsnell@ARM.com virtual void regProbePoints(); 16410023Smatt.horsnell@ARM.com 16510023Smatt.horsnell@ARM.com /** 16610023Smatt.horsnell@ARM.com * Register probe listeners for this object. 16710023Smatt.horsnell@ARM.com */ 16810023Smatt.horsnell@ARM.com virtual void regProbeListeners(); 16910023Smatt.horsnell@ARM.com 17010023Smatt.horsnell@ARM.com /** 17110023Smatt.horsnell@ARM.com * Get the probe manager for this object. 17210023Smatt.horsnell@ARM.com */ 17310023Smatt.horsnell@ARM.com ProbeManager *getProbeManager(); 17410023Smatt.horsnell@ARM.com 17510023Smatt.horsnell@ARM.com /** 1767532Ssteve.reinhardt@amd.com * startup() is the final initialization call before simulation. 1777532Ssteve.reinhardt@amd.com * All state is initialized (including unserialized state, if any, 1787823Ssteve.reinhardt@amd.com * such as the curTick() value), so this is the appropriate place to 1797532Ssteve.reinhardt@amd.com * schedule initial event(s) for objects that need them. 1807532Ssteve.reinhardt@amd.com */ 1817492Ssteve.reinhardt@amd.com virtual void startup(); 182330SN/A 1839196SAndreas.Sandberg@arm.com /** 1849342SAndreas.Sandberg@arm.com * Provide a default implementation of the drain interface that 1859342SAndreas.Sandberg@arm.com * simply returns 0 (draining completed) and sets the drain state 1869342SAndreas.Sandberg@arm.com * to Drained. 1879342SAndreas.Sandberg@arm.com */ 1889342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *drainManger); 1899342SAndreas.Sandberg@arm.com 19010911Sandreas.sandberg@arm.com /** 19110911Sandreas.sandberg@arm.com * Write back dirty buffers to memory using functional writes. 19210911Sandreas.sandberg@arm.com * 19310911Sandreas.sandberg@arm.com * After returning, an object implementing this method should have 19410911Sandreas.sandberg@arm.com * written all its dirty data back to memory. This method is 19510911Sandreas.sandberg@arm.com * typically used to prepare a system with caches for 19610911Sandreas.sandberg@arm.com * checkpointing. 19710911Sandreas.sandberg@arm.com */ 19810911Sandreas.sandberg@arm.com virtual void memWriteback() {}; 19910911Sandreas.sandberg@arm.com 20010911Sandreas.sandberg@arm.com /** 20110911Sandreas.sandberg@arm.com * Invalidate the contents of memory buffers. 20210911Sandreas.sandberg@arm.com * 20310911Sandreas.sandberg@arm.com * When the switching to hardware virtualized CPU models, we need 20410911Sandreas.sandberg@arm.com * to make sure that we don't have any cached state in the system 20510911Sandreas.sandberg@arm.com * that might become stale when we return. This method is used to 20610911Sandreas.sandberg@arm.com * flush all such state back to main memory. 20710911Sandreas.sandberg@arm.com * 20810911Sandreas.sandberg@arm.com * @warn This does <i>not</i> cause any dirty state to be written 20910911Sandreas.sandberg@arm.com * back to memory. 21010911Sandreas.sandberg@arm.com */ 21110911Sandreas.sandberg@arm.com virtual void memInvalidate() {}; 21210905Sandreas.sandberg@arm.com 21310905Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE {}; 21410905Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE {}; 21510905Sandreas.sandberg@arm.com 2169342SAndreas.Sandberg@arm.com /** 2179196SAndreas.Sandberg@arm.com * Serialize all SimObjects in the system. 2189196SAndreas.Sandberg@arm.com */ 21910905Sandreas.sandberg@arm.com static void serializeAll(CheckpointOut &cp); 220938SN/A 2211031SN/A#ifdef DEBUG 2221031SN/A public: 2231031SN/A bool doDebugBreak; 2241031SN/A static void debugObjectBreak(const std::string &objs); 2251031SN/A#endif 2261031SN/A 2275314Sstever@gmail.com /** 2285314Sstever@gmail.com * Find the SimObject with the given name and return a pointer to 2295315Sstever@gmail.com * it. Primarily used for interactive debugging. Argument is 2305314Sstever@gmail.com * char* rather than std::string to make it callable from gdb. 2315314Sstever@gmail.com */ 2325314Sstever@gmail.com static SimObject *find(const char *name); 2332SN/A}; 2342SN/A 2359554Sandreas.hansson@arm.com#ifdef DEBUG 2369554Sandreas.hansson@arm.comvoid debugObjectBreak(const char *objs); 2379554Sandreas.hansson@arm.com#endif 2389554Sandreas.hansson@arm.com 2392SN/A#endif // __SIM_OBJECT_HH__ 240