sim_object.cc revision 6216:2f4020838149
111986Sandreas.sandberg@arm.com/*
211986Sandreas.sandberg@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan
311986Sandreas.sandberg@arm.com * All rights reserved.
411986Sandreas.sandberg@arm.com *
511986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without
611986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are
711986Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright
811986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer;
911986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright
1011986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the
1111986Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution;
1212391Sjason@lowepower.com * neither the name of the copyright holders nor the names of its
1312391Sjason@lowepower.com * contributors may be used to endorse or promote products derived from
1411986Sandreas.sandberg@arm.com * this software without specific prior written permission.
1511986Sandreas.sandberg@arm.com *
1611986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1711986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1811986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1911986Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2011986Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2112037Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2212037Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2312037Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2412037Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2512037Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2612037Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2712037Sandreas.sandberg@arm.com *
2812037Sandreas.sandberg@arm.com * Authors: Steve Reinhardt
2912037Sandreas.sandberg@arm.com *          Nathan Binkert
3011986Sandreas.sandberg@arm.com */
3111986Sandreas.sandberg@arm.com
3211986Sandreas.sandberg@arm.com#include <cassert>
3311986Sandreas.sandberg@arm.com
3411986Sandreas.sandberg@arm.com#include "base/callback.hh"
3511986Sandreas.sandberg@arm.com#include "base/inifile.hh"
3611986Sandreas.sandberg@arm.com#include "base/match.hh"
3711986Sandreas.sandberg@arm.com#include "base/misc.hh"
3811986Sandreas.sandberg@arm.com#include "base/stats/events.hh"
3911986Sandreas.sandberg@arm.com#include "base/trace.hh"
4011986Sandreas.sandberg@arm.com#include "base/types.hh"
4111986Sandreas.sandberg@arm.com#include "sim/sim_object.hh"
4211986Sandreas.sandberg@arm.com#include "sim/stats.hh"
4311986Sandreas.sandberg@arm.com
4411986Sandreas.sandberg@arm.comusing namespace std;
4511986Sandreas.sandberg@arm.com
4611986Sandreas.sandberg@arm.com
4711986Sandreas.sandberg@arm.com////////////////////////////////////////////////////////////////////////
4811986Sandreas.sandberg@arm.com//
4911986Sandreas.sandberg@arm.com// SimObject member definitions
5011986Sandreas.sandberg@arm.com//
5111986Sandreas.sandberg@arm.com////////////////////////////////////////////////////////////////////////
5212391Sjason@lowepower.com
5312391Sjason@lowepower.com//
5412391Sjason@lowepower.com// static list of all SimObjects, used for initialization etc.
5512391Sjason@lowepower.com//
5612391Sjason@lowepower.comSimObject::SimObjectList SimObject::simObjectList;
5711986Sandreas.sandberg@arm.com
5811986Sandreas.sandberg@arm.com//
5911986Sandreas.sandberg@arm.com// SimObject constructor: used to maintain static simObjectList
6011986Sandreas.sandberg@arm.com//
6112391Sjason@lowepower.comSimObject::SimObject(const Params *p)
62    : EventManager(p->eventq), _params(p)
63{
64#ifdef DEBUG
65    doDebugBreak = false;
66#endif
67
68    simObjectList.push_back(this);
69    state = Running;
70}
71
72void
73SimObject::init()
74{
75}
76
77//
78// no default statistics, so nothing to do in base implementation
79//
80void
81SimObject::regStats()
82{
83}
84
85void
86SimObject::regFormulas()
87{
88}
89
90void
91SimObject::resetStats()
92{
93}
94
95//
96// static function:
97//   call regStats() on all SimObjects and then regFormulas() on all
98//   SimObjects.
99//
100struct SimObjectResetCB : public Callback
101{
102    virtual void process() { SimObject::resetAllStats(); }
103};
104
105namespace {
106    static SimObjectResetCB StatResetCB;
107}
108
109void
110SimObject::regAllStats()
111{
112    SimObjectList::iterator i;
113    SimObjectList::iterator end = simObjectList.end();
114
115    /**
116     * @todo change cprintfs to DPRINTFs
117     */
118    for (i = simObjectList.begin(); i != end; ++i) {
119#ifdef STAT_DEBUG
120        cprintf("registering stats for %s\n", (*i)->name());
121#endif
122        (*i)->regStats();
123    }
124
125    for (i = simObjectList.begin(); i != end; ++i) {
126#ifdef STAT_DEBUG
127        cprintf("registering formulas for %s\n", (*i)->name());
128#endif
129        (*i)->regFormulas();
130    }
131
132    Stats::registerResetCallback(&StatResetCB);
133}
134
135//
136// static function: call init() on all SimObjects.
137//
138void
139SimObject::initAll()
140{
141    SimObjectList::iterator i = simObjectList.begin();
142    SimObjectList::iterator end = simObjectList.end();
143
144    for (; i != end; ++i) {
145        SimObject *obj = *i;
146        obj->init();
147    }
148}
149
150//
151// static function: call resetStats() on all SimObjects.
152//
153void
154SimObject::resetAllStats()
155{
156    SimObjectList::iterator i = simObjectList.begin();
157    SimObjectList::iterator end = simObjectList.end();
158
159    for (; i != end; ++i) {
160        SimObject *obj = *i;
161        obj->resetStats();
162    }
163}
164
165//
166// static function: serialize all SimObjects.
167//
168void
169SimObject::serializeAll(ostream &os)
170{
171    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
172    SimObjectList::reverse_iterator rend = simObjectList.rend();
173
174    for (; ri != rend; ++ri) {
175        SimObject *obj = *ri;
176        obj->nameOut(os);
177        obj->serialize(os);
178   }
179}
180
181void
182SimObject::unserializeAll(Checkpoint *cp)
183{
184    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
185    SimObjectList::reverse_iterator rend = simObjectList.rend();
186
187    for (; ri != rend; ++ri) {
188        SimObject *obj = *ri;
189        DPRINTFR(Config, "Unserializing '%s'\n",
190                 obj->name());
191        if(cp->sectionExists(obj->name()))
192            obj->unserialize(cp, obj->name());
193        else
194            warn("Not unserializing '%s': no section found in checkpoint.\n",
195                 obj->name());
196   }
197}
198
199#ifdef DEBUG
200//
201// static function: flag which objects should have the debugger break
202//
203void
204SimObject::debugObjectBreak(const string &objs)
205{
206    SimObjectList::const_iterator i = simObjectList.begin();
207    SimObjectList::const_iterator end = simObjectList.end();
208
209    ObjectMatch match(objs);
210    for (; i != end; ++i) {
211        SimObject *obj = *i;
212        obj->doDebugBreak = match.match(obj->name());
213   }
214}
215
216void
217debugObjectBreak(const char *objs)
218{
219    SimObject::debugObjectBreak(string(objs));
220}
221#endif
222
223void
224SimObject::recordEvent(const std::string &stat)
225{
226    Stats::recordEvent(stat);
227}
228
229unsigned int
230SimObject::drain(Event *drain_event)
231{
232    state = Drained;
233    return 0;
234}
235
236void
237SimObject::resume()
238{
239    state = Running;
240}
241
242void
243SimObject::setMemoryMode(State new_mode)
244{
245    panic("setMemoryMode() should only be called on systems");
246}
247
248void
249SimObject::switchOut()
250{
251    panic("Unimplemented!");
252}
253
254void
255SimObject::takeOverFrom(BaseCPU *cpu)
256{
257    panic("Unimplemented!");
258}
259
260
261SimObject *
262SimObject::find(const char *name)
263{
264    SimObjectList::const_iterator i = simObjectList.begin();
265    SimObjectList::const_iterator end = simObjectList.end();
266
267    for (; i != end; ++i) {
268        SimObject *obj = *i;
269        if (obj->name() == name)
270            return obj;
271    }
272
273    return NULL;
274}
275