sim_object.cc revision 2840:227f7c4f8c81
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 322SN/A#include <assert.h> 332SN/A 342SN/A#include "base/callback.hh" 354046Sbinkertn@umich.edu#include "base/inifile.hh" 364046Sbinkertn@umich.edu#include "base/match.hh" 3756SN/A#include "base/misc.hh" 384776Sgblack@eecs.umich.edu#include "base/trace.hh" 395034Smilesck@eecs.umich.edu#include "base/stats/events.hh" 402SN/A#include "sim/host.hh" 413064Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 422SN/A#include "sim/stats.hh" 432SN/A#include "sim/param.hh" 442SN/A 452SN/Ausing namespace std; 464776Sgblack@eecs.umich.edu 472SN/A 482SN/A//////////////////////////////////////////////////////////////////////// 494776Sgblack@eecs.umich.edu// 504776Sgblack@eecs.umich.edu// SimObject member definitions 514776Sgblack@eecs.umich.edu// 522SN/A//////////////////////////////////////////////////////////////////////// 532SN/A 542SN/A// 554046Sbinkertn@umich.edu// static list of all SimObjects, used for initialization etc. 562SN/A// 572SN/ASimObject::SimObjectList SimObject::simObjectList; 584776Sgblack@eecs.umich.edu 594776Sgblack@eecs.umich.edunamespace Stats { 604776Sgblack@eecs.umich.edu extern ObjectMatch event_ignore; 615034Smilesck@eecs.umich.edu} 625034Smilesck@eecs.umich.edu 634776Sgblack@eecs.umich.edu// 642SN/A// SimObject constructor: used to maintain static simObjectList 654776Sgblack@eecs.umich.edu// 664776Sgblack@eecs.umich.eduSimObject::SimObject(Params *p) 674776Sgblack@eecs.umich.edu : _params(p) 684776Sgblack@eecs.umich.edu{ 694776Sgblack@eecs.umich.edu#ifdef DEBUG 704776Sgblack@eecs.umich.edu doDebugBreak = false; 712SN/A#endif 724776Sgblack@eecs.umich.edu 734776Sgblack@eecs.umich.edu doRecordEvent = !Stats::event_ignore.match(name()); 742SN/A simObjectList.push_back(this); 754776Sgblack@eecs.umich.edu state = Atomic; 764776Sgblack@eecs.umich.edu} 774074Sbinkertn@umich.edu 784776Sgblack@eecs.umich.edu// 794776Sgblack@eecs.umich.edu// SimObject constructor: used to maintain static simObjectList 804776Sgblack@eecs.umich.edu// 814776Sgblack@eecs.umich.eduSimObject::SimObject(const string &_name) 822SN/A : _params(new Params) 834054Sbinkertn@umich.edu{ 842SN/A _params->name = _name; 852SN/A#ifdef DEBUG 86 doDebugBreak = false; 87#endif 88 89 doRecordEvent = !Stats::event_ignore.match(name()); 90 simObjectList.push_back(this); 91 state = Atomic; 92} 93 94void 95SimObject::connect() 96{ 97} 98 99void 100SimObject::init() 101{ 102} 103 104// 105// no default statistics, so nothing to do in base implementation 106// 107void 108SimObject::regStats() 109{ 110} 111 112void 113SimObject::regFormulas() 114{ 115} 116 117void 118SimObject::resetStats() 119{ 120} 121 122// 123// static function: 124// call regStats() on all SimObjects and then regFormulas() on all 125// SimObjects. 126// 127struct SimObjectResetCB : public Callback 128{ 129 virtual void process() { SimObject::resetAllStats(); } 130}; 131 132namespace { 133 static SimObjectResetCB StatResetCB; 134} 135 136void 137SimObject::regAllStats() 138{ 139 SimObjectList::iterator i; 140 SimObjectList::iterator end = simObjectList.end(); 141 142 /** 143 * @todo change cprintfs to DPRINTFs 144 */ 145 for (i = simObjectList.begin(); i != end; ++i) { 146#ifdef STAT_DEBUG 147 cprintf("registering stats for %s\n", (*i)->name()); 148#endif 149 (*i)->regStats(); 150 } 151 152 for (i = simObjectList.begin(); i != end; ++i) { 153#ifdef STAT_DEBUG 154 cprintf("registering formulas for %s\n", (*i)->name()); 155#endif 156 (*i)->regFormulas(); 157 } 158 159 Stats::registerResetCallback(&StatResetCB); 160} 161 162// 163// static function: call connect() on all SimObjects. 164// 165void 166SimObject::connectAll() 167{ 168 SimObjectList::iterator i = simObjectList.begin(); 169 SimObjectList::iterator end = simObjectList.end(); 170 171 for (; i != end; ++i) { 172 SimObject *obj = *i; 173 obj->connect(); 174 } 175} 176 177// 178// static function: call init() on all SimObjects. 179// 180void 181SimObject::initAll() 182{ 183 SimObjectList::iterator i = simObjectList.begin(); 184 SimObjectList::iterator end = simObjectList.end(); 185 186 for (; i != end; ++i) { 187 SimObject *obj = *i; 188 obj->init(); 189 } 190} 191 192// 193// static function: call resetStats() on all SimObjects. 194// 195void 196SimObject::resetAllStats() 197{ 198 SimObjectList::iterator i = simObjectList.begin(); 199 SimObjectList::iterator end = simObjectList.end(); 200 201 for (; i != end; ++i) { 202 SimObject *obj = *i; 203 obj->resetStats(); 204 } 205} 206 207// 208// static function: serialize all SimObjects. 209// 210void 211SimObject::serializeAll(ostream &os) 212{ 213 SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 214 SimObjectList::reverse_iterator rend = simObjectList.rend(); 215 216 for (; ri != rend; ++ri) { 217 SimObject *obj = *ri; 218 obj->nameOut(os); 219 obj->serialize(os); 220 } 221} 222 223void 224SimObject::unserializeAll(Checkpoint *cp) 225{ 226 SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 227 SimObjectList::reverse_iterator rend = simObjectList.rend(); 228 229 for (; ri != rend; ++ri) { 230 SimObject *obj = *ri; 231 DPRINTFR(Config, "Unserializing '%s'\n", 232 obj->name()); 233 if(cp->sectionExists(obj->name())) 234 obj->unserialize(cp, obj->name()); 235 else 236 warn("Not unserializing '%s': no section found in checkpoint.\n", 237 obj->name()); 238 } 239} 240 241#ifdef DEBUG 242// 243// static function: flag which objects should have the debugger break 244// 245void 246SimObject::debugObjectBreak(const string &objs) 247{ 248 SimObjectList::const_iterator i = simObjectList.begin(); 249 SimObjectList::const_iterator end = simObjectList.end(); 250 251 ObjectMatch match(objs); 252 for (; i != end; ++i) { 253 SimObject *obj = *i; 254 obj->doDebugBreak = match.match(obj->name()); 255 } 256} 257 258void 259debugObjectBreak(const char *objs) 260{ 261 SimObject::debugObjectBreak(string(objs)); 262} 263#endif 264 265void 266SimObject::recordEvent(const std::string &stat) 267{ 268 if (doRecordEvent) 269 Stats::recordEvent(stat); 270} 271 272bool 273SimObject::drain(Event *drain_event) 274{ 275 if (state != DrainedAtomic && state != Atomic) { 276 panic("Must implement your own drain function if it is to be used " 277 "in timing mode!"); 278 } 279 state = DrainedAtomic; 280 return false; 281} 282 283void 284SimObject::resume() 285{ 286 if (state == DrainedAtomic) { 287 state = Atomic; 288 } else if (state == DrainedTiming) { 289 state = Timing; 290 } 291} 292 293void 294SimObject::setMemoryMode(State new_mode) 295{ 296 assert(new_mode == Timing || new_mode == Atomic); 297 if (state == DrainedAtomic && new_mode == Timing) { 298 state = DrainedTiming; 299 } else if (state == DrainedTiming && new_mode == Atomic) { 300 state = DrainedAtomic; 301 } else { 302 state = new_mode; 303 } 304} 305 306void 307SimObject::switchOut() 308{ 309 panic("Unimplemented!"); 310} 311 312void 313SimObject::takeOverFrom(BaseCPU *cpu) 314{ 315 panic("Unimplemented!"); 316} 317 318DEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject) 319