sim_object.cc revision 11793:ef606668d247 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 *          Nathan Binkert
31 */
32
33#include "sim/sim_object.hh"
34
35#include <cassert>
36
37#include "base/callback.hh"
38#include "base/inifile.hh"
39#include "base/match.hh"
40#include "base/misc.hh"
41#include "base/trace.hh"
42#include "base/types.hh"
43#include "debug/Checkpoint.hh"
44#include "sim/probe/probe.hh"
45#include "sim/stats.hh"
46
47using namespace std;
48
49
50////////////////////////////////////////////////////////////////////////
51//
52// SimObject member definitions
53//
54////////////////////////////////////////////////////////////////////////
55
56//
57// static list of all SimObjects, used for initialization etc.
58//
59SimObject::SimObjectList SimObject::simObjectList;
60
61//
62// SimObject constructor: used to maintain static simObjectList
63//
64SimObject::SimObject(const Params *p)
65    : EventManager(getEventQueue(p->eventq_index)), _params(p)
66{
67#ifdef DEBUG
68    doDebugBreak = false;
69#endif
70    simObjectList.push_back(this);
71    probeManager = new ProbeManager(this);
72}
73
74SimObject::~SimObject()
75{
76    delete probeManager;
77}
78
79void
80SimObject::init()
81{
82}
83
84void
85SimObject::loadState(CheckpointIn &cp)
86{
87    if (cp.sectionExists(name())) {
88        DPRINTF(Checkpoint, "unserializing\n");
89        // This works despite name() returning a fully qualified name
90        // since we are at the top level.
91        unserializeSection(cp, name());
92    } else {
93        DPRINTF(Checkpoint, "no checkpoint section found\n");
94    }
95}
96
97void
98SimObject::initState()
99{
100}
101
102void
103SimObject::startup()
104{
105}
106
107//
108// no default statistics, so nothing to do in base implementation
109//
110void
111SimObject::regStats()
112{
113}
114
115void
116SimObject::resetStats()
117{
118}
119
120/**
121 * No probe points by default, so do nothing in base.
122 */
123void
124SimObject::regProbePoints()
125{
126}
127
128/**
129 * No probe listeners by default, so do nothing in base.
130 */
131void
132SimObject::regProbeListeners()
133{
134}
135
136ProbeManager *
137SimObject::getProbeManager()
138{
139    return probeManager;
140}
141
142//
143// static function: serialize all SimObjects.
144//
145void
146SimObject::serializeAll(CheckpointOut &cp)
147{
148    SimObjectList::reverse_iterator ri = simObjectList.rbegin();
149    SimObjectList::reverse_iterator rend = simObjectList.rend();
150
151    for (; ri != rend; ++ri) {
152        SimObject *obj = *ri;
153        // This works despite name() returning a fully qualified name
154        // since we are at the top level.
155        obj->serializeSection(cp, obj->name());
156   }
157}
158
159
160#ifdef DEBUG
161//
162// static function: flag which objects should have the debugger break
163//
164void
165SimObject::debugObjectBreak(const string &objs)
166{
167    SimObjectList::const_iterator i = simObjectList.begin();
168    SimObjectList::const_iterator end = simObjectList.end();
169
170    ObjectMatch match(objs);
171    for (; i != end; ++i) {
172        SimObject *obj = *i;
173        obj->doDebugBreak = match.match(obj->name());
174   }
175}
176
177void
178debugObjectBreak(const char *objs)
179{
180    SimObject::debugObjectBreak(string(objs));
181}
182#endif
183
184SimObject *
185SimObject::find(const char *name)
186{
187    SimObjectList::const_iterator i = simObjectList.begin();
188    SimObjectList::const_iterator end = simObjectList.end();
189
190    for (; i != end; ++i) {
191        SimObject *obj = *i;
192        if (obj->name() == name)
193            return obj;
194    }
195
196    return NULL;
197}
198