sim_events.hh revision 2665
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292SN/A */ 302SN/A 311798SN/A#ifndef __SIM_SIM_EVENTS_HH__ 321798SN/A#define __SIM_SIM_EVENTS_HH__ 332SN/A 3456SN/A#include "sim/eventq.hh" 352SN/A 362SN/A// 372SN/A// Event to terminate simulation at a particular cycle/instruction 382SN/A// 392SN/Aclass SimExitEvent : public Event 402SN/A{ 412SN/A private: 422SN/A // string explaining why we're terminating 432SN/A std::string cause; 442SN/A int code; 452SN/A 462SN/A public: 472SN/A SimExitEvent(const std::string &_cause, int c = 0) 48396SN/A : Event(&mainEventQueue, Sim_Exit_Pri), cause(_cause), 492SN/A code(c) 50396SN/A { schedule(curTick); } 512SN/A 522SN/A SimExitEvent(Tick _when, const std::string &_cause, int c = 0) 53396SN/A : Event(&mainEventQueue, Sim_Exit_Pri), cause(_cause), 542SN/A code(c) 55396SN/A { schedule(_when); } 562SN/A 572SN/A SimExitEvent(EventQueue *q, const std::string &_cause, int c = 0) 58396SN/A : Event(q, Sim_Exit_Pri), cause(_cause), code(c) 59396SN/A { schedule(curTick); } 602SN/A 612SN/A SimExitEvent(EventQueue *q, Tick _when, const std::string &_cause, 622SN/A int c = 0) 63396SN/A : Event(q, Sim_Exit_Pri), cause(_cause), code(c) 64396SN/A { schedule(_when); } 652SN/A 662SN/A void process(); // process event 672SN/A 682SN/A virtual const char *description(); 692SN/A}; 702SN/A 712SN/A// 722SN/A// Event class to terminate simulation after 'n' related events have 732SN/A// occurred using a shared counter: used to terminate when *all* 742SN/A// threads have reached a particular instruction count 752SN/A// 762SN/Aclass CountedExitEvent : public Event 772SN/A{ 782SN/A private: 792SN/A std::string cause; // string explaining why we're terminating 802SN/A int &downCounter; // decrement & terminate if zero 812SN/A 822SN/A public: 832SN/A CountedExitEvent(EventQueue *q, const std::string &_cause, 842SN/A Tick _when, int &_downCounter); 852SN/A 862SN/A void process(); // process event 872SN/A 882SN/A virtual const char *description(); 892SN/A}; 902SN/A 912SN/A// 921798SN/A// Event to check swap usage 932SN/A// 942SN/Aclass CheckSwapEvent : public Event 952SN/A{ 962SN/A private: 972SN/A int interval; 982SN/A 992SN/A public: 1002SN/A CheckSwapEvent(EventQueue *q, int ival) 1012SN/A : Event(q), interval(ival) 1021798SN/A { schedule(curTick + interval); } 1032SN/A 1042SN/A void process(); // process event 1052SN/A 1062SN/A virtual const char *description(); 1072SN/A}; 1082SN/A 1091798SN/A// 1101798SN/A// Progress event: print out cycle every so often so we know we're 1111798SN/A// making forward progress. 1121798SN/A// 1131798SN/Aclass ProgressEvent : public Event 1141798SN/A{ 1151798SN/A protected: 1161798SN/A Tick interval; 1171798SN/A 1181798SN/A public: 1191798SN/A ProgressEvent(EventQueue *q, Tick ival) 1201798SN/A : Event(q), interval(ival) 1211798SN/A { schedule(curTick + interval); } 1221798SN/A 1231798SN/A void process(); // process event 1241798SN/A 1251798SN/A virtual const char *description(); 1261798SN/A}; 1271798SN/A 1281798SN/A#endif // __SIM_SIM_EVENTS_HH__ 129