faults.cc revision 4183
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Gabe Black 302SN/A */ 312SN/A 322SN/A#include "arch/isa_traits.hh" 332SN/A#include "base/misc.hh" 342SN/A#include "cpu/thread_context.hh" 352147SN/A#include "cpu/base.hh" 367678Sgblack@eecs.umich.edu#include "sim/faults.hh" 378229Snate@binkert.org#include "sim/process.hh" 388229Snate@binkert.org#include "mem/page_table.hh" 397878Sgblack@eecs.umich.edu 402147SN/A#if !FULL_SYSTEM 412147SN/Avoid FaultBase::invoke(ThreadContext * tc) 422680Sktlim@umich.edu{ 432132SN/A fatal("fault (%s) detected @ PC %p", name(), tc->readPC()); 442147SN/A} 455999Snate@binkert.org#else 462147SN/Avoid FaultBase::invoke(ThreadContext * tc) 472147SN/A{ 482147SN/A DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), tc->readPC()); 492147SN/A tc->getCpuPtr()->recordEvent(csprintf("Fault %s", name())); 502147SN/A 512147SN/A assert(!tc->misspeculating()); 522147SN/A} 532147SN/A#endif 542147SN/A 552090SN/Avoid UnimpFault::invoke(ThreadContext * tc) 562147SN/A{ 574695Sgblack@eecs.umich.edu panic("Unimpfault: %s\n", panicStr.c_str()); 587678Sgblack@eecs.umich.edu} 597678Sgblack@eecs.umich.edu 604695Sgblack@eecs.umich.eduvoid PageTableFault::invoke(ThreadContext *tc) 614695Sgblack@eecs.umich.edu{ 622SN/A Process *p = tc->getProcessPtr(); 632SN/A 642612SN/A // We've accessed the next page of the stack, so extend the stack 652612SN/A // to cover it. 662612SN/A if(vaddr < p->stack_min && vaddr >= p->stack_min - TheISA::PageBytes) 672612SN/A { 682612SN/A p->stack_min -= TheISA::PageBytes; 692612SN/A if(p->stack_base - p->stack_min > 8*1024*1024) 702612SN/A fatal("Over max stack size for one thread\n"); 712612SN/A p->pTable->allocate(p->stack_min, TheISA::PageBytes); 722612SN/A warn("Increasing stack size by one page."); 734695Sgblack@eecs.umich.edu } 747678Sgblack@eecs.umich.edu // Otherwise, we have an unexpected page fault. Report that fact, 757678Sgblack@eecs.umich.edu // and what address was accessed to cause the fault. 762612SN/A else 772612SN/A { 788545Ssaidi@eecs.umich.edu panic("Page table fault when accessing virtual address %#x\n", vaddr); 798545Ssaidi@eecs.umich.edu } 808545Ssaidi@eecs.umich.edu} 818545Ssaidi@eecs.umich.edu