dot_writer.py revision 9853:20c07aa9322c 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Hansson
37#          Uri Wiener
38
39#####################################################################
40#
41# System visualization using DOT
42#
43# While config.ini and config.json provide an almost complete listing
44# of a system's components and connectivity, they lack a birds-eye
45# view. The output generated by do_dot() is a DOT-based figure (as a
46# pdf and an editable svg file) and its source dot code. Nodes are
47# components, and edges represent the memory hierarchy: the edges are
48# directed, from a master to slave. Initially all nodes are
49# generated, and then all edges are added. do_dot should be called
50# with the top-most SimObject (namely root but not necessarily), the
51# output folder and the output dot source filename. From the given
52# node, both processes (node and edge creation) is performed
53# recursivly, traversing all children of the given root.
54#
55# pydot is required. When missing, no output will be generated.
56#
57#####################################################################
58
59import m5, os, re
60from m5.SimObject import isRoot, isSimObjectVector
61from m5.util import warn
62try:
63    import pydot
64except:
65    pydot = False
66
67# need to create all nodes (components) before creating edges (memory channels)
68def dot_create_nodes(simNode, callgraph):
69    if isRoot(simNode):
70        label = "root"
71    else:
72        label = simNode._name
73    full_path = re.sub('\.', '_', simNode.path())
74    # add class name under the label
75    label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\""
76
77    # each component is a sub-graph (cluster)
78    cluster = dot_create_cluster(simNode, full_path, label)
79
80    # create nodes per port
81    for port_name in simNode._ports.keys():
82        port = simNode._port_refs.get(port_name, None)
83        if port != None:
84            full_port_name = full_path + "_" + port_name
85            port_node = dot_create_node(simNode, full_port_name, port_name)
86            cluster.add_node(port_node)
87
88    # recurse to children
89    if simNode._children:
90        for c in simNode._children:
91            child = simNode._children[c]
92            if isSimObjectVector(child):
93                for obj in child:
94                    dot_create_nodes(obj, cluster)
95            else:
96                dot_create_nodes(child, cluster)
97
98    callgraph.add_subgraph(cluster)
99
100# create all edges according to memory hierarchy
101def dot_create_edges(simNode, callgraph):
102    for port_name in simNode._ports.keys():
103        port = simNode._port_refs.get(port_name, None)
104        if port != None:
105            full_path = re.sub('\.', '_', simNode.path())
106            full_port_name = full_path + "_" + port_name
107            port_node = dot_create_node(simNode, full_port_name, port_name)
108            # create edges
109            if type(port) is m5.params.PortRef:
110                dot_add_edge(simNode, callgraph, full_port_name, port)
111            else:
112                for p in port.elements:
113                    dot_add_edge(simNode, callgraph, full_port_name, p)
114
115    # recurse to children
116    if simNode._children:
117        for c in simNode._children:
118            child = simNode._children[c]
119            if isSimObjectVector(child):
120                for obj in child:
121                    dot_create_edges(obj, callgraph)
122            else:
123                dot_create_edges(child, callgraph)
124
125def dot_add_edge(simNode, callgraph, full_port_name, peerPort):
126    if peerPort.role == "MASTER":
127        peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \
128                + "." + peerPort.peer.name)
129        callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name))
130
131def dot_create_cluster(simNode, full_path, label):
132    return pydot.Cluster( \
133                         full_path, \
134                         shape = "Mrecord", \
135                         label = label, \
136                         style = "\"rounded, filled\"", \
137                         color = "#000000", \
138                         fillcolor = dot_gen_colour(simNode), \
139                         fontname = "Arial", \
140                         fontsize = "14", \
141                         fontcolor = "#000000" \
142                         )
143
144def dot_create_node(simNode, full_path, label):
145    return pydot.Node( \
146                         full_path, \
147                         shape = "Mrecord", \
148                         label = label, \
149                         style = "\"rounded, filled\"", \
150                         color = "#000000", \
151                         fillcolor = dot_gen_colour(simNode, True), \
152                         fontname = "Arial", \
153                         fontsize = "14", \
154                         fontcolor = "#000000" \
155                         )
156
157# an enumerator for different kinds of node types, at the moment we
158# discern the majority of node types, with the caches being the
159# notable exception
160class NodeType:
161    SYS = 0
162    CPU = 1
163    BUS = 2
164    MEM = 3
165    DEV = 4
166    OTHER = 5
167
168# based on the sim object, determine the node type
169def get_node_type(simNode):
170    if isinstance(simNode, m5.objects.System):
171        return NodeType.SYS
172    # NULL ISA has no BaseCPU or PioDevice, so check if these names
173    # exists before using them
174    elif 'BaseCPU' in dir(m5.objects) and \
175            isinstance(simNode, m5.objects.BaseCPU):
176        return NodeType.CPU
177    elif 'PioDevice' in dir(m5.objects) and \
178            isinstance(simNode, m5.objects.PioDevice):
179        return NodeType.DEV
180    elif isinstance(simNode, m5.objects.BaseBus):
181        return NodeType.BUS
182    elif isinstance(simNode, m5.objects.AbstractMemory):
183        return NodeType.MEM
184    else:
185        return NodeType.OTHER
186
187# based on the node type, determine the colour as an RGB tuple, the
188# palette is rather arbitrary at this point (some coherent natural
189# tones), and someone that feels artistic should probably have a look
190def get_type_colour(nodeType):
191    if nodeType == NodeType.SYS:
192        return (228, 231, 235)
193    elif nodeType == NodeType.CPU:
194        return (187, 198, 217)
195    elif nodeType == NodeType.BUS:
196        return (111, 121, 140)
197    elif nodeType == NodeType.MEM:
198        return (94, 89, 88)
199    elif nodeType == NodeType.DEV:
200        return (199, 167, 147)
201    elif nodeType == NodeType.OTHER:
202        # use a relatively gray shade
203        return (186, 182, 174)
204
205# generate colour for a node, either corresponding to a sim object or a
206# port
207def dot_gen_colour(simNode, isPort = False):
208    # determine the type of the current node, and also its parent, if
209    # the node is not the same type as the parent then we use the base
210    # colour for its type
211    node_type = get_node_type(simNode)
212    if simNode._parent:
213        parent_type = get_node_type(simNode._parent)
214    else:
215        parent_type = NodeType.OTHER
216
217    # if this node is the same type as the parent, then scale the
218    # colour based on the depth such that the deeper levels in the
219    # hierarchy get darker colours
220    if node_type == parent_type:
221        # start out with a depth of zero
222        depth = 0
223        parent = simNode._parent
224        # find the closes parent that is not the same type
225        while parent and get_node_type(parent) == parent_type:
226            depth = depth + 1
227            parent = parent._parent
228        node_colour = get_type_colour(parent_type)
229        # slightly arbitrary, but assume that the depth is less than
230        # five levels
231        r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour)
232    else:
233        node_colour = get_type_colour(node_type)
234        r, g, b = node_colour
235
236    # if we are colouring a port, then make it a slightly darker shade
237    # than the node that encapsulates it, once again use a magic constant
238    if isPort:
239        r, g, b = map(lambda x: 0.8 * x, (r, g, b))
240
241    return dot_rgb_to_html(r, g, b)
242
243def dot_rgb_to_html(r, g, b):
244    return "#%.2x%.2x%.2x" % (r, g, b)
245
246def do_dot(root, outdir, dotFilename):
247    if not pydot:
248        return
249    # * use ranksep > 1.0 for for vertical separation between nodes
250    # especially useful if you need to annotate edges using e.g. visio
251    # which accepts svg format
252    # * no need for hoizontal separation as nothing moves horizonally
253    callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3')
254    dot_create_nodes(root, callgraph)
255    dot_create_edges(root, callgraph)
256    dot_filename = os.path.join(outdir, dotFilename)
257    callgraph.write(dot_filename)
258    try:
259        # dot crashes if the figure is extremely wide.
260        # So avoid terminating simulation unnecessarily
261        callgraph.write_svg(dot_filename + ".svg")
262        callgraph.write_pdf(dot_filename + ".pdf")
263    except:
264        warn("failed to generate dot output from %s", dot_filename)
265