dot_writer.py revision 9852:16046705aa55
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Uri Wiener 38 39##################################################################### 40# 41# System visualization using DOT 42# 43# While config.ini and config.json provide an almost complete listing 44# of a system's components and connectivity, they lack a birds-eye 45# view. The output generated by do_dot() is a DOT-based figure (as a 46# pdf and an editable svg file) and its source dot code. Nodes are 47# components, and edges represent the memory hierarchy: the edges are 48# directed, from a master to slave. Initially all nodes are 49# generated, and then all edges are added. do_dot should be called 50# with the top-most SimObject (namely root but not necessarily), the 51# output folder and the output dot source filename. From the given 52# node, both processes (node and edge creation) is performed 53# recursivly, traversing all children of the given root. 54# 55# pydot is required. When missing, no output will be generated. 56# 57##################################################################### 58 59import m5, os, re 60from m5.SimObject import isRoot, isSimObjectVector 61from m5.util import warn 62try: 63 import pydot 64except: 65 pydot = False 66 67# need to create all nodes (components) before creating edges (memory channels) 68def dot_create_nodes(simNode, callgraph): 69 if isRoot(simNode): 70 label = "root" 71 else: 72 label = simNode._name 73 full_path = re.sub('\.', '_', simNode.path()) 74 # add class name under the label 75 label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 76 77 # each component is a sub-graph (cluster) 78 cluster = dot_create_cluster(simNode, full_path, label) 79 80 # create nodes per port 81 for port_name in simNode._ports.keys(): 82 port = simNode._port_refs.get(port_name, None) 83 if port != None: 84 full_port_name = full_path + "_" + port_name 85 port_node = dot_create_node(simNode, full_port_name, port_name) 86 cluster.add_node(port_node) 87 88 # recurse to children 89 if simNode._children: 90 for c in simNode._children: 91 child = simNode._children[c] 92 if isSimObjectVector(child): 93 for obj in child: 94 dot_create_nodes(obj, cluster) 95 else: 96 dot_create_nodes(child, cluster) 97 98 callgraph.add_subgraph(cluster) 99 100# create all edges according to memory hierarchy 101def dot_create_edges(simNode, callgraph): 102 for port_name in simNode._ports.keys(): 103 port = simNode._port_refs.get(port_name, None) 104 if port != None: 105 full_path = re.sub('\.', '_', simNode.path()) 106 full_port_name = full_path + "_" + port_name 107 port_node = dot_create_node(simNode, full_port_name, port_name) 108 # create edges 109 if type(port) is m5.params.PortRef: 110 dot_add_edge(simNode, callgraph, full_port_name, port) 111 else: 112 for p in port.elements: 113 dot_add_edge(simNode, callgraph, full_port_name, p) 114 115 # recurse to children 116 if simNode._children: 117 for c in simNode._children: 118 child = simNode._children[c] 119 if isSimObjectVector(child): 120 for obj in child: 121 dot_create_edges(obj, callgraph) 122 else: 123 dot_create_edges(child, callgraph) 124 125def dot_add_edge(simNode, callgraph, full_port_name, peerPort): 126 if peerPort.role == "MASTER": 127 peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \ 128 + "." + peerPort.peer.name) 129 callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name)) 130 131def dot_create_cluster(simNode, full_path, label): 132 # if you read this, feel free to modify colors / style 133 return pydot.Cluster( \ 134 full_path, \ 135 shape = "Mrecord", \ 136 label = label, \ 137 style = "\"rounded, filled\"", \ 138 color = "#000000", \ 139 fillcolor = dot_gen_color(simNode), \ 140 fontname = "Arial", \ 141 fontsize = "14", \ 142 fontcolor = "#000000" \ 143 ) 144 145def dot_create_node(simNode, full_path, label): 146 # if you read this, feel free to modify colors / style. 147 # leafs may have a different style => seperate function 148 return pydot.Node( \ 149 full_path, \ 150 shape = "Mrecord", \ 151 label = label, \ 152 style = "\"rounded, filled\"", \ 153 color = "#000000", \ 154 fillcolor = "#808080", \ 155 fontname = "Arial", \ 156 fontsize = "14", \ 157 fontcolor = "#000000" \ 158 ) 159 160# generate color for nodes 161def dot_gen_color(simNode): 162 # start off with white 163 base = (256, 256, 256) 164 # scale the color based on the depth 165 depth = len(simNode.path().split('.')) 166 # slightly arbitrary, but assume that the depth is less than six 167 # levels 168 r, g, b = map(lambda x: x * max(1 - depth / 6.0, 0.3), base) 169 170 return dot_rgb_to_html(r, g, b) 171 172def dot_rgb_to_html(r, g, b): 173 return "#%.2x%.2x%.2x" % (r, g, b) 174 175def do_dot(root, outdir, dotFilename): 176 if not pydot: 177 return 178 # * use ranksep > 1.0 for for vertical separation between nodes 179 # especially useful if you need to annotate edges using e.g. visio 180 # which accepts svg format 181 # * no need for hoizontal separation as nothing moves horizonally 182 callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 183 dot_create_nodes(root, callgraph) 184 dot_create_edges(root, callgraph) 185 dot_filename = os.path.join(outdir, dotFilename) 186 callgraph.write(dot_filename) 187 try: 188 # dot crashes if the figure is extremely wide. 189 # So avoid terminating simulation unnecessarily 190 callgraph.write_svg(dot_filename + ".svg") 191 callgraph.write_pdf(dot_filename + ".pdf") 192 except: 193 warn("failed to generate pdf output from %s", dot_filename) 194