dot_writer.py revision 9528:d05714c2ab9c
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Uri Wiener 38 39##################################################################### 40# 41# System visualization using DOT 42# 43# While config.ini and config.json provide an almost complete listing 44# of a system's components and connectivity, they lack a birds-eye view. 45# The output generated by do_dot() is a DOT-based figure (pdf) and its 46# source dot code. Nodes are components, and edges represent 47# the memory hierarchy: the edges are directed, from a master to a slave. 48# Initially all nodes are generated, and then all edges are added. 49# do_dot should be called with the top-most SimObject (namely root 50# but not necessarily), the output folder and the output dot source 51# filename. From the given node, both processes (node and edge creation) 52# is performed recursivly, traversing all children of the given root. 53# 54# pydot is required. When missing, no output will be generated. 55# 56##################################################################### 57 58import m5, os, re 59from m5.SimObject import isRoot, isSimObjectVector 60from m5.util import warn 61try: 62 import pydot 63except: 64 pydot = False 65 66# need to create all nodes (components) before creating edges (memory channels) 67def dot_create_nodes(simNode, callgraph): 68 if isRoot(simNode): 69 label = "root" 70 else: 71 label = simNode._name 72 full_path = re.sub('\.', '_', simNode.path()) 73 74 # each component is a sub-graph (cluster) 75 cluster = dot_create_cluster(simNode, full_path, label) 76 77 # create nodes per port 78 for port_name in simNode._ports.keys(): 79 port = simNode._port_refs.get(port_name, None) 80 if port != None: 81 full_port_name = full_path + "_" + port_name 82 port_node = dot_create_node(simNode, full_port_name, port_name) 83 cluster.add_node(port_node) 84 85 # recurse to children 86 if simNode._children: 87 for c in simNode._children: 88 child = simNode._children[c] 89 if isSimObjectVector(child): 90 for obj in child: 91 dot_create_nodes(obj, cluster) 92 else: 93 dot_create_nodes(child, cluster) 94 95 callgraph.add_subgraph(cluster) 96 97# create all edges according to memory hierarchy 98def dot_create_edges(simNode, callgraph): 99 for port_name in simNode._ports.keys(): 100 port = simNode._port_refs.get(port_name, None) 101 if port != None: 102 full_path = re.sub('\.', '_', simNode.path()) 103 full_port_name = full_path + "_" + port_name 104 port_node = dot_create_node(simNode, full_port_name, port_name) 105 # create edges 106 if type(port) is m5.params.PortRef: 107 dot_add_edge(simNode, callgraph, full_port_name, port) 108 else: 109 for p in port.elements: 110 dot_add_edge(simNode, callgraph, full_port_name, p) 111 112 # recurse to children 113 if simNode._children: 114 for c in simNode._children: 115 child = simNode._children[c] 116 if isSimObjectVector(child): 117 for obj in child: 118 dot_create_edges(obj, callgraph) 119 else: 120 dot_create_edges(child, callgraph) 121 122def dot_add_edge(simNode, callgraph, full_port_name, peerPort): 123 if peerPort.role == "MASTER": 124 peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \ 125 + "." + peerPort.peer.name) 126 callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name)) 127 128def dot_create_cluster(simNode, full_path, label): 129 # if you read this, feel free to modify colors / style 130 return pydot.Cluster( \ 131 full_path, \ 132 shape = "Mrecord", \ 133 label = label, \ 134 style = "\"rounded, filled\"", \ 135 color = "#000000", \ 136 fillcolor = dot_gen_color(simNode), \ 137 fontname = "Arial", \ 138 fontsize = "14", \ 139 fontcolor = "#000000" \ 140 ) 141 142def dot_create_node(simNode, full_path, label): 143 # if you read this, feel free to modify colors / style. 144 # leafs may have a different style => seperate function 145 return pydot.Node( \ 146 full_path, \ 147 shape = "Mrecord", \ 148 label = label, \ 149 style = "\"rounded, filled\"", \ 150 color = "#000000", \ 151 fillcolor = "#808080", \ 152 fontname = "Arial", \ 153 fontsize = "14", \ 154 fontcolor = "#000000" \ 155 ) 156 157# generate color for nodes 158# currently a simple grayscale. placeholder for aesthetic programmers. 159def dot_gen_color(simNode): 160 depth = len(simNode.path().split('.')) 161 depth = 256 - depth * 16 * 3 162 return dot_rgb_to_html(simNode, depth, depth, depth) 163 164def dot_rgb_to_html(simNode, r, g, b): 165 return "#%.2x%.2x%.2x" % (r, g, b) 166 167def do_dot(root, outdir, dotFilename): 168 if not pydot: 169 return 170 callgraph = pydot.Dot(graph_type='digraph') 171 dot_create_nodes(root, callgraph) 172 dot_create_edges(root, callgraph) 173 dot_filename = os.path.join(outdir, dotFilename) 174 callgraph.write(dot_filename) 175 try: 176 # dot crashes if the figure is extremely wide. 177 # So avoid terminating simulation unnecessarily 178 callgraph.write_pdf(dot_filename + ".pdf") 179 except: 180 warn("failed to generate pdf output from %s", dot_filename) 181