dot_writer.py revision 13714:35636064b7a1
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Uri Wiener 38# Sascha Bischoff 39 40##################################################################### 41# 42# System visualization using DOT 43# 44# While config.ini and config.json provide an almost complete listing 45# of a system's components and connectivity, they lack a birds-eye 46# view. The output generated by do_dot() is a DOT-based figure (as a 47# pdf and an editable svg file) and its source dot code. Nodes are 48# components, and edges represent the memory hierarchy: the edges are 49# directed, from a master to slave. Initially all nodes are 50# generated, and then all edges are added. do_dot should be called 51# with the top-most SimObject (namely root but not necessarily), the 52# output folder and the output dot source filename. From the given 53# node, both processes (node and edge creation) is performed 54# recursivly, traversing all children of the given root. 55# 56# pydot is required. When missing, no output will be generated. 57# 58##################################################################### 59 60from __future__ import print_function 61from __future__ import absolute_import 62 63import m5, os, re 64from m5.SimObject import isRoot, isSimObjectVector 65from m5.params import PortRef, isNullPointer 66from m5.util import warn 67try: 68 import pydot 69except: 70 pydot = False 71 72def simnode_children(simNode): 73 for child in simNode._children.values(): 74 if isNullPointer(child): 75 continue 76 if isSimObjectVector(child): 77 for obj in child: 78 if not isNullPointer(obj): 79 yield obj 80 else: 81 yield child 82 83# need to create all nodes (components) before creating edges (memory channels) 84def dot_create_nodes(simNode, callgraph): 85 if isRoot(simNode): 86 label = "root" 87 else: 88 label = simNode._name 89 full_path = re.sub('\.', '_', simNode.path()) 90 # add class name under the label 91 label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 92 93 # each component is a sub-graph (cluster) 94 cluster = dot_create_cluster(simNode, full_path, label) 95 96 # create nodes per port 97 for port_name in simNode._ports.keys(): 98 port = simNode._port_refs.get(port_name, None) 99 if port != None: 100 full_port_name = full_path + "_" + port_name 101 port_node = dot_create_node(simNode, full_port_name, port_name) 102 cluster.add_node(port_node) 103 104 # recurse to children 105 for child in simnode_children(simNode): 106 dot_create_nodes(child, cluster) 107 108 callgraph.add_subgraph(cluster) 109 110# create all edges according to memory hierarchy 111def dot_create_edges(simNode, callgraph): 112 for port_name in simNode._ports.keys(): 113 port = simNode._port_refs.get(port_name, None) 114 if port != None: 115 full_path = re.sub('\.', '_', simNode.path()) 116 full_port_name = full_path + "_" + port_name 117 port_node = dot_create_node(simNode, full_port_name, port_name) 118 # create edges 119 if isinstance(port, PortRef): 120 dot_add_edge(simNode, callgraph, full_port_name, port) 121 else: 122 for p in port.elements: 123 dot_add_edge(simNode, callgraph, full_port_name, p) 124 125 # recurse to children 126 for child in simnode_children(simNode): 127 dot_create_edges(child, callgraph) 128 129def dot_add_edge(simNode, callgraph, full_port_name, peerPort): 130 if peerPort.role == "MASTER": 131 peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \ 132 + "." + peerPort.peer.name) 133 callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name)) 134 135def dot_create_cluster(simNode, full_path, label): 136 # get the parameter values of the node and use them as a tooltip 137 ini_strings = [] 138 for param in sorted(simNode._params.keys()): 139 value = simNode._values.get(param) 140 if value != None: 141 # parameter name = value in HTML friendly format 142 ini_strings.append(str(param) + "=" + 143 simNode._values[param].ini_str()) 144 # join all the parameters with an HTML newline 145 tooltip = " ".join(ini_strings) 146 147 return pydot.Cluster( \ 148 full_path, \ 149 shape = "Mrecord", \ 150 label = label, \ 151 tooltip = "\"" + tooltip + "\"", \ 152 style = "\"rounded, filled\"", \ 153 color = "#000000", \ 154 fillcolor = dot_gen_colour(simNode), \ 155 fontname = "Arial", \ 156 fontsize = "14", \ 157 fontcolor = "#000000" \ 158 ) 159 160def dot_create_node(simNode, full_path, label): 161 return pydot.Node( \ 162 full_path, \ 163 shape = "Mrecord", \ 164 label = label, \ 165 style = "\"rounded, filled\"", \ 166 color = "#000000", \ 167 fillcolor = dot_gen_colour(simNode, True), \ 168 fontname = "Arial", \ 169 fontsize = "14", \ 170 fontcolor = "#000000" \ 171 ) 172 173# an enumerator for different kinds of node types, at the moment we 174# discern the majority of node types, with the caches being the 175# notable exception 176class NodeType: 177 SYS = 0 178 CPU = 1 179 XBAR = 2 180 MEM = 3 181 DEV = 4 182 OTHER = 5 183 184# based on the sim object, determine the node type 185def get_node_type(simNode): 186 if isinstance(simNode, m5.objects.System): 187 return NodeType.SYS 188 # NULL ISA has no BaseCPU or PioDevice, so check if these names 189 # exists before using them 190 elif 'BaseCPU' in dir(m5.objects) and \ 191 isinstance(simNode, m5.objects.BaseCPU): 192 return NodeType.CPU 193 elif 'PioDevice' in dir(m5.objects) and \ 194 isinstance(simNode, m5.objects.PioDevice): 195 return NodeType.DEV 196 elif isinstance(simNode, m5.objects.BaseXBar): 197 return NodeType.XBAR 198 elif isinstance(simNode, m5.objects.AbstractMemory): 199 return NodeType.MEM 200 else: 201 return NodeType.OTHER 202 203# based on the node type, determine the colour as an RGB tuple, the 204# palette is rather arbitrary at this point (some coherent natural 205# tones), and someone that feels artistic should probably have a look 206def get_type_colour(nodeType): 207 if nodeType == NodeType.SYS: 208 return (228, 231, 235) 209 elif nodeType == NodeType.CPU: 210 return (187, 198, 217) 211 elif nodeType == NodeType.XBAR: 212 return (111, 121, 140) 213 elif nodeType == NodeType.MEM: 214 return (94, 89, 88) 215 elif nodeType == NodeType.DEV: 216 return (199, 167, 147) 217 elif nodeType == NodeType.OTHER: 218 # use a relatively gray shade 219 return (186, 182, 174) 220 221# generate colour for a node, either corresponding to a sim object or a 222# port 223def dot_gen_colour(simNode, isPort = False): 224 # determine the type of the current node, and also its parent, if 225 # the node is not the same type as the parent then we use the base 226 # colour for its type 227 node_type = get_node_type(simNode) 228 if simNode._parent: 229 parent_type = get_node_type(simNode._parent) 230 else: 231 parent_type = NodeType.OTHER 232 233 # if this node is the same type as the parent, then scale the 234 # colour based on the depth such that the deeper levels in the 235 # hierarchy get darker colours 236 if node_type == parent_type: 237 # start out with a depth of zero 238 depth = 0 239 parent = simNode._parent 240 # find the closes parent that is not the same type 241 while parent and get_node_type(parent) == parent_type: 242 depth = depth + 1 243 parent = parent._parent 244 node_colour = get_type_colour(parent_type) 245 # slightly arbitrary, but assume that the depth is less than 246 # five levels 247 r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour) 248 else: 249 node_colour = get_type_colour(node_type) 250 r, g, b = node_colour 251 252 # if we are colouring a port, then make it a slightly darker shade 253 # than the node that encapsulates it, once again use a magic constant 254 if isPort: 255 r, g, b = map(lambda x: 0.8 * x, (r, g, b)) 256 257 return dot_rgb_to_html(r, g, b) 258 259def dot_rgb_to_html(r, g, b): 260 return "#%.2x%.2x%.2x" % (r, g, b) 261 262# We need to create all of the clock domains. We abuse the alpha channel to get 263# the correct domain colouring. 264def dot_add_clk_domain(c_dom, v_dom): 265 label = "\"" + str(c_dom) + "\ :\ " + str(v_dom) + "\"" 266 label = re.sub('\.', '_', str(label)) 267 full_path = re.sub('\.', '_', str(c_dom)) 268 return pydot.Cluster( \ 269 full_path, \ 270 shape = "Mrecord", \ 271 label = label, \ 272 style = "\"rounded, filled, dashed\"", \ 273 color = "#000000", \ 274 fillcolor = "#AFC8AF8F", \ 275 fontname = "Arial", \ 276 fontsize = "14", \ 277 fontcolor = "#000000" \ 278 ) 279 280def dot_create_dvfs_nodes(simNode, callgraph, domain=None): 281 if isRoot(simNode): 282 label = "root" 283 else: 284 label = simNode._name 285 full_path = re.sub('\.', '_', simNode.path()) 286 # add class name under the label 287 label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 288 289 # each component is a sub-graph (cluster) 290 cluster = dot_create_cluster(simNode, full_path, label) 291 292 # create nodes per port 293 for port_name in simNode._ports.keys(): 294 port = simNode._port_refs.get(port_name, None) 295 if port != None: 296 full_port_name = full_path + "_" + port_name 297 port_node = dot_create_node(simNode, full_port_name, port_name) 298 cluster.add_node(port_node) 299 300 # Dictionary of DVFS domains 301 dvfs_domains = {} 302 303 # recurse to children 304 for child in simnode_children(simNode): 305 try: 306 c_dom = child.__getattr__('clk_domain') 307 v_dom = c_dom.__getattr__('voltage_domain') 308 except AttributeError: 309 # Just re-use the domain from above 310 c_dom = domain 311 v_dom = c_dom.__getattr__('voltage_domain') 312 pass 313 314 if c_dom == domain or c_dom == None: 315 dot_create_dvfs_nodes(child, cluster, domain) 316 else: 317 if c_dom not in dvfs_domains: 318 dvfs_cluster = dot_add_clk_domain(c_dom, v_dom) 319 dvfs_domains[c_dom] = dvfs_cluster 320 else: 321 dvfs_cluster = dvfs_domains[c_dom] 322 dot_create_dvfs_nodes(child, dvfs_cluster, c_dom) 323 324 for key in dvfs_domains: 325 cluster.add_subgraph(dvfs_domains[key]) 326 327 callgraph.add_subgraph(cluster) 328 329def do_dot(root, outdir, dotFilename): 330 if not pydot: 331 return 332 # * use ranksep > 1.0 for for vertical separation between nodes 333 # especially useful if you need to annotate edges using e.g. visio 334 # which accepts svg format 335 # * no need for hoizontal separation as nothing moves horizonally 336 callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 337 dot_create_nodes(root, callgraph) 338 dot_create_edges(root, callgraph) 339 dot_filename = os.path.join(outdir, dotFilename) 340 callgraph.write(dot_filename) 341 try: 342 # dot crashes if the figure is extremely wide. 343 # So avoid terminating simulation unnecessarily 344 callgraph.write_svg(dot_filename + ".svg") 345 callgraph.write_pdf(dot_filename + ".pdf") 346 except: 347 warn("failed to generate dot output from %s", dot_filename) 348 349def do_dvfs_dot(root, outdir, dotFilename): 350 if not pydot: 351 return 352 353 # There is a chance that we are unable to resolve the clock or 354 # voltage domains. If so, we fail silently. 355 try: 356 dvfsgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 357 dot_create_dvfs_nodes(root, dvfsgraph) 358 dot_create_edges(root, dvfsgraph) 359 dot_filename = os.path.join(outdir, dotFilename) 360 dvfsgraph.write(dot_filename) 361 except: 362 warn("Failed to generate dot graph for DVFS domains") 363 return 364 365 try: 366 # dot crashes if the figure is extremely wide. 367 # So avoid terminating simulation unnecessarily 368 dvfsgraph.write_svg(dot_filename + ".svg") 369 dvfsgraph.write_pdf(dot_filename + ".pdf") 370 except: 371 warn("failed to generate dot output from %s", dot_filename) 372