dot_writer.py revision 13709:dd6b7ac5801f 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Hansson
37#          Uri Wiener
38#          Sascha Bischoff
39
40#####################################################################
41#
42# System visualization using DOT
43#
44# While config.ini and config.json provide an almost complete listing
45# of a system's components and connectivity, they lack a birds-eye
46# view. The output generated by do_dot() is a DOT-based figure (as a
47# pdf and an editable svg file) and its source dot code. Nodes are
48# components, and edges represent the memory hierarchy: the edges are
49# directed, from a master to slave. Initially all nodes are
50# generated, and then all edges are added. do_dot should be called
51# with the top-most SimObject (namely root but not necessarily), the
52# output folder and the output dot source filename. From the given
53# node, both processes (node and edge creation) is performed
54# recursivly, traversing all children of the given root.
55#
56# pydot is required. When missing, no output will be generated.
57#
58#####################################################################
59
60import m5, os, re
61from m5.SimObject import isRoot, isSimObjectVector
62from m5.params import PortRef, isNullPointer
63from m5.util import warn
64try:
65    import pydot
66except:
67    pydot = False
68
69def simnode_children(simNode):
70    for child in simNode._children.values():
71        if isNullPointer(child):
72            continue
73        if isSimObjectVector(child):
74            for obj in child:
75                if not isNullPointer(obj):
76                    yield obj
77        else:
78            yield child
79
80# need to create all nodes (components) before creating edges (memory channels)
81def dot_create_nodes(simNode, callgraph):
82    if isRoot(simNode):
83        label = "root"
84    else:
85        label = simNode._name
86    full_path = re.sub('\.', '_', simNode.path())
87    # add class name under the label
88    label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\""
89
90    # each component is a sub-graph (cluster)
91    cluster = dot_create_cluster(simNode, full_path, label)
92
93    # create nodes per port
94    for port_name in simNode._ports.keys():
95        port = simNode._port_refs.get(port_name, None)
96        if port != None:
97            full_port_name = full_path + "_" + port_name
98            port_node = dot_create_node(simNode, full_port_name, port_name)
99            cluster.add_node(port_node)
100
101    # recurse to children
102    for child in simnode_children(simNode):
103        dot_create_nodes(child, cluster)
104
105    callgraph.add_subgraph(cluster)
106
107# create all edges according to memory hierarchy
108def dot_create_edges(simNode, callgraph):
109    for port_name in simNode._ports.keys():
110        port = simNode._port_refs.get(port_name, None)
111        if port != None:
112            full_path = re.sub('\.', '_', simNode.path())
113            full_port_name = full_path + "_" + port_name
114            port_node = dot_create_node(simNode, full_port_name, port_name)
115            # create edges
116            if isinstance(port, PortRef):
117                dot_add_edge(simNode, callgraph, full_port_name, port)
118            else:
119                for p in port.elements:
120                    dot_add_edge(simNode, callgraph, full_port_name, p)
121
122    # recurse to children
123    for child in simnode_children(simNode):
124        dot_create_edges(child, callgraph)
125
126def dot_add_edge(simNode, callgraph, full_port_name, peerPort):
127    if peerPort.role == "MASTER":
128        peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \
129                + "." + peerPort.peer.name)
130        callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name))
131
132def dot_create_cluster(simNode, full_path, label):
133    # get the parameter values of the node and use them as a tooltip
134    ini_strings = []
135    for param in sorted(simNode._params.keys()):
136        value = simNode._values.get(param)
137        if value != None:
138            # parameter name = value in HTML friendly format
139            ini_strings.append(str(param) + "=" +
140                               simNode._values[param].ini_str())
141    # join all the parameters with an HTML newline
142    tooltip = "
".join(ini_strings)
143
144    return pydot.Cluster( \
145                         full_path, \
146                         shape = "Mrecord", \
147                         label = label, \
148                         tooltip = "\"" + tooltip + "\"", \
149                         style = "\"rounded, filled\"", \
150                         color = "#000000", \
151                         fillcolor = dot_gen_colour(simNode), \
152                         fontname = "Arial", \
153                         fontsize = "14", \
154                         fontcolor = "#000000" \
155                         )
156
157def dot_create_node(simNode, full_path, label):
158    return pydot.Node( \
159                         full_path, \
160                         shape = "Mrecord", \
161                         label = label, \
162                         style = "\"rounded, filled\"", \
163                         color = "#000000", \
164                         fillcolor = dot_gen_colour(simNode, True), \
165                         fontname = "Arial", \
166                         fontsize = "14", \
167                         fontcolor = "#000000" \
168                         )
169
170# an enumerator for different kinds of node types, at the moment we
171# discern the majority of node types, with the caches being the
172# notable exception
173class NodeType:
174    SYS = 0
175    CPU = 1
176    XBAR = 2
177    MEM = 3
178    DEV = 4
179    OTHER = 5
180
181# based on the sim object, determine the node type
182def get_node_type(simNode):
183    if isinstance(simNode, m5.objects.System):
184        return NodeType.SYS
185    # NULL ISA has no BaseCPU or PioDevice, so check if these names
186    # exists before using them
187    elif 'BaseCPU' in dir(m5.objects) and \
188            isinstance(simNode, m5.objects.BaseCPU):
189        return NodeType.CPU
190    elif 'PioDevice' in dir(m5.objects) and \
191            isinstance(simNode, m5.objects.PioDevice):
192        return NodeType.DEV
193    elif isinstance(simNode, m5.objects.BaseXBar):
194        return NodeType.XBAR
195    elif isinstance(simNode, m5.objects.AbstractMemory):
196        return NodeType.MEM
197    else:
198        return NodeType.OTHER
199
200# based on the node type, determine the colour as an RGB tuple, the
201# palette is rather arbitrary at this point (some coherent natural
202# tones), and someone that feels artistic should probably have a look
203def get_type_colour(nodeType):
204    if nodeType == NodeType.SYS:
205        return (228, 231, 235)
206    elif nodeType == NodeType.CPU:
207        return (187, 198, 217)
208    elif nodeType == NodeType.XBAR:
209        return (111, 121, 140)
210    elif nodeType == NodeType.MEM:
211        return (94, 89, 88)
212    elif nodeType == NodeType.DEV:
213        return (199, 167, 147)
214    elif nodeType == NodeType.OTHER:
215        # use a relatively gray shade
216        return (186, 182, 174)
217
218# generate colour for a node, either corresponding to a sim object or a
219# port
220def dot_gen_colour(simNode, isPort = False):
221    # determine the type of the current node, and also its parent, if
222    # the node is not the same type as the parent then we use the base
223    # colour for its type
224    node_type = get_node_type(simNode)
225    if simNode._parent:
226        parent_type = get_node_type(simNode._parent)
227    else:
228        parent_type = NodeType.OTHER
229
230    # if this node is the same type as the parent, then scale the
231    # colour based on the depth such that the deeper levels in the
232    # hierarchy get darker colours
233    if node_type == parent_type:
234        # start out with a depth of zero
235        depth = 0
236        parent = simNode._parent
237        # find the closes parent that is not the same type
238        while parent and get_node_type(parent) == parent_type:
239            depth = depth + 1
240            parent = parent._parent
241        node_colour = get_type_colour(parent_type)
242        # slightly arbitrary, but assume that the depth is less than
243        # five levels
244        r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour)
245    else:
246        node_colour = get_type_colour(node_type)
247        r, g, b = node_colour
248
249    # if we are colouring a port, then make it a slightly darker shade
250    # than the node that encapsulates it, once again use a magic constant
251    if isPort:
252        r, g, b = map(lambda x: 0.8 * x, (r, g, b))
253
254    return dot_rgb_to_html(r, g, b)
255
256def dot_rgb_to_html(r, g, b):
257    return "#%.2x%.2x%.2x" % (r, g, b)
258
259# We need to create all of the clock domains. We abuse the alpha channel to get
260# the correct domain colouring.
261def dot_add_clk_domain(c_dom, v_dom):
262    label = "\"" + str(c_dom) + "\ :\ " + str(v_dom) + "\""
263    label = re.sub('\.', '_', str(label))
264    full_path = re.sub('\.', '_', str(c_dom))
265    return pydot.Cluster( \
266                     full_path, \
267                     shape = "Mrecord", \
268                     label = label, \
269                     style = "\"rounded, filled, dashed\"", \
270                     color = "#000000", \
271                     fillcolor = "#AFC8AF8F", \
272                     fontname = "Arial", \
273                     fontsize = "14", \
274                     fontcolor = "#000000" \
275                     )
276
277def dot_create_dvfs_nodes(simNode, callgraph, domain=None):
278    if isRoot(simNode):
279        label = "root"
280    else:
281        label = simNode._name
282    full_path = re.sub('\.', '_', simNode.path())
283    # add class name under the label
284    label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\""
285
286    # each component is a sub-graph (cluster)
287    cluster = dot_create_cluster(simNode, full_path, label)
288
289    # create nodes per port
290    for port_name in simNode._ports.keys():
291        port = simNode._port_refs.get(port_name, None)
292        if port != None:
293            full_port_name = full_path + "_" + port_name
294            port_node = dot_create_node(simNode, full_port_name, port_name)
295            cluster.add_node(port_node)
296
297    # Dictionary of DVFS domains
298    dvfs_domains = {}
299
300    # recurse to children
301    for child in simnode_children(simNode):
302        try:
303            c_dom = child.__getattr__('clk_domain')
304            v_dom = c_dom.__getattr__('voltage_domain')
305        except AttributeError:
306            # Just re-use the domain from above
307            c_dom = domain
308            v_dom = c_dom.__getattr__('voltage_domain')
309            pass
310
311        if c_dom == domain or c_dom == None:
312            dot_create_dvfs_nodes(child, cluster, domain)
313        else:
314            if c_dom not in dvfs_domains:
315                dvfs_cluster = dot_add_clk_domain(c_dom, v_dom)
316                dvfs_domains[c_dom] = dvfs_cluster
317            else:
318                dvfs_cluster = dvfs_domains[c_dom]
319            dot_create_dvfs_nodes(child, dvfs_cluster, c_dom)
320
321    for key in dvfs_domains:
322        cluster.add_subgraph(dvfs_domains[key])
323
324    callgraph.add_subgraph(cluster)
325
326def do_dot(root, outdir, dotFilename):
327    if not pydot:
328        return
329    # * use ranksep > 1.0 for for vertical separation between nodes
330    # especially useful if you need to annotate edges using e.g. visio
331    # which accepts svg format
332    # * no need for hoizontal separation as nothing moves horizonally
333    callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3')
334    dot_create_nodes(root, callgraph)
335    dot_create_edges(root, callgraph)
336    dot_filename = os.path.join(outdir, dotFilename)
337    callgraph.write(dot_filename)
338    try:
339        # dot crashes if the figure is extremely wide.
340        # So avoid terminating simulation unnecessarily
341        callgraph.write_svg(dot_filename + ".svg")
342        callgraph.write_pdf(dot_filename + ".pdf")
343    except:
344        warn("failed to generate dot output from %s", dot_filename)
345
346def do_dvfs_dot(root, outdir, dotFilename):
347    if not pydot:
348        return
349
350    # There is a chance that we are unable to resolve the clock or
351    # voltage domains. If so, we fail silently.
352    try:
353        dvfsgraph = pydot.Dot(graph_type='digraph', ranksep='1.3')
354        dot_create_dvfs_nodes(root, dvfsgraph)
355        dot_create_edges(root, dvfsgraph)
356        dot_filename = os.path.join(outdir, dotFilename)
357        dvfsgraph.write(dot_filename)
358    except:
359        warn("Failed to generate dot graph for DVFS domains")
360        return
361
362    try:
363        # dot crashes if the figure is extremely wide.
364        # So avoid terminating simulation unnecessarily
365        dvfsgraph.write_svg(dot_filename + ".svg")
366        dvfsgraph.write_pdf(dot_filename + ".pdf")
367    except:
368        warn("failed to generate dot output from %s", dot_filename)
369