dot_writer.py revision 8999
18999Suri.wiener@arm.com# Copyright (c) 2012 ARM Limited 28999Suri.wiener@arm.com# All rights reserved. 38999Suri.wiener@arm.com# 48999Suri.wiener@arm.com# The license below extends only to copyright in the software and shall 58999Suri.wiener@arm.com# not be construed as granting a license to any other intellectual 68999Suri.wiener@arm.com# property including but not limited to intellectual property relating 78999Suri.wiener@arm.com# to a hardware implementation of the functionality of the software 88999Suri.wiener@arm.com# licensed hereunder. You may use the software subject to the license 98999Suri.wiener@arm.com# terms below provided that you ensure that this notice is replicated 108999Suri.wiener@arm.com# unmodified and in its entirety in all distributions of the software, 118999Suri.wiener@arm.com# modified or unmodified, in source code or in binary form. 128999Suri.wiener@arm.com# 138999Suri.wiener@arm.com# Redistribution and use in source and binary forms, with or without 148999Suri.wiener@arm.com# modification, are permitted provided that the following conditions are 158999Suri.wiener@arm.com# met: redistributions of source code must retain the above copyright 168999Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer; 178999Suri.wiener@arm.com# redistributions in binary form must reproduce the above copyright 188999Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer in the 198999Suri.wiener@arm.com# documentation and/or other materials provided with the distribution; 208999Suri.wiener@arm.com# neither the name of the copyright holders nor the names of its 218999Suri.wiener@arm.com# contributors may be used to endorse or promote products derived from 228999Suri.wiener@arm.com# this software without specific prior written permission. 238999Suri.wiener@arm.com# 248999Suri.wiener@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 258999Suri.wiener@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 268999Suri.wiener@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 278999Suri.wiener@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 288999Suri.wiener@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 298999Suri.wiener@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 308999Suri.wiener@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 318999Suri.wiener@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 328999Suri.wiener@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 338999Suri.wiener@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 348999Suri.wiener@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 358999Suri.wiener@arm.com# 368999Suri.wiener@arm.com# Authors: Andreas Hansson 378999Suri.wiener@arm.com# Uri Wiener 388999Suri.wiener@arm.com 398999Suri.wiener@arm.com##################################################################### 408999Suri.wiener@arm.com# 418999Suri.wiener@arm.com# System visualization using DOT 428999Suri.wiener@arm.com# 438999Suri.wiener@arm.com# While config.ini and config.json provide an almost complete listing 448999Suri.wiener@arm.com# of a system's components and connectivity, they lack a birds-eye view. 458999Suri.wiener@arm.com# The output generated by do_dot() is a DOT-based figure (pdf) and its 468999Suri.wiener@arm.com# source dot code. Nodes are components, and edges represent 478999Suri.wiener@arm.com# the memory hierarchy: the edges are directed, from a master to a slave. 488999Suri.wiener@arm.com# Initially all nodes are generated, and then all edges are added. 498999Suri.wiener@arm.com# do_dot should be called with the top-most SimObject (namely root 508999Suri.wiener@arm.com# but not necessarily), the output folder and the output dot source 518999Suri.wiener@arm.com# filename. From the given node, both processes (node and edge creation) 528999Suri.wiener@arm.com# is performed recursivly, traversing all children of the given root. 538999Suri.wiener@arm.com# 548999Suri.wiener@arm.com# pydot is required. When missing, no output will be generated. 558999Suri.wiener@arm.com# 568999Suri.wiener@arm.com##################################################################### 578999Suri.wiener@arm.com 588999Suri.wiener@arm.comimport m5, os, re 598999Suri.wiener@arm.comfrom m5.SimObject import isRoot, isSimObjectVector 608999Suri.wiener@arm.comtry: 618999Suri.wiener@arm.com import pydot 628999Suri.wiener@arm.comexcept: 638999Suri.wiener@arm.com pydot = False 648999Suri.wiener@arm.com 658999Suri.wiener@arm.com# need to create all nodes (components) before creating edges (memory channels) 668999Suri.wiener@arm.comdef dot_create_nodes(simNode, callgraph): 678999Suri.wiener@arm.com if isRoot(simNode): 688999Suri.wiener@arm.com label = "root" 698999Suri.wiener@arm.com else: 708999Suri.wiener@arm.com label = simNode._name 718999Suri.wiener@arm.com full_path = re.sub('\.', '_', simNode.path()) 728999Suri.wiener@arm.com 738999Suri.wiener@arm.com # each component is a sub-graph (cluster) 748999Suri.wiener@arm.com cluster = dot_create_cluster(simNode, full_path, label) 758999Suri.wiener@arm.com 768999Suri.wiener@arm.com # create nodes per port 778999Suri.wiener@arm.com for port_name in simNode._ports.keys(): 788999Suri.wiener@arm.com port = simNode._port_refs.get(port_name, None) 798999Suri.wiener@arm.com if port != None: 808999Suri.wiener@arm.com full_port_name = full_path + "_" + port_name 818999Suri.wiener@arm.com port_node = dot_create_node(simNode, full_port_name, port_name) 828999Suri.wiener@arm.com cluster.add_node(port_node) 838999Suri.wiener@arm.com 848999Suri.wiener@arm.com # recurse to children 858999Suri.wiener@arm.com if simNode._children: 868999Suri.wiener@arm.com for c in simNode._children: 878999Suri.wiener@arm.com child = simNode._children[c] 888999Suri.wiener@arm.com if isSimObjectVector(child): 898999Suri.wiener@arm.com for obj in child: 908999Suri.wiener@arm.com dot_create_nodes(obj, cluster) 918999Suri.wiener@arm.com else: 928999Suri.wiener@arm.com dot_create_nodes(child, cluster) 938999Suri.wiener@arm.com 948999Suri.wiener@arm.com callgraph.add_subgraph(cluster) 958999Suri.wiener@arm.com 968999Suri.wiener@arm.com# create all edges according to memory hierarchy 978999Suri.wiener@arm.comdef dot_create_edges(simNode, callgraph): 988999Suri.wiener@arm.com for port_name in simNode._ports.keys(): 998999Suri.wiener@arm.com port = simNode._port_refs.get(port_name, None) 1008999Suri.wiener@arm.com if port != None: 1018999Suri.wiener@arm.com full_path = re.sub('\.', '_', simNode.path()) 1028999Suri.wiener@arm.com full_port_name = full_path + "_" + port_name 1038999Suri.wiener@arm.com port_node = dot_create_node(simNode, full_port_name, port_name) 1048999Suri.wiener@arm.com # create edges 1058999Suri.wiener@arm.com if type(port) is m5.params.PortRef: 1068999Suri.wiener@arm.com dot_add_edge(simNode, callgraph, full_port_name, port) 1078999Suri.wiener@arm.com else: 1088999Suri.wiener@arm.com for p in port.elements: 1098999Suri.wiener@arm.com dot_add_edge(simNode, callgraph, full_port_name, p) 1108999Suri.wiener@arm.com 1118999Suri.wiener@arm.com # recurse to children 1128999Suri.wiener@arm.com if simNode._children: 1138999Suri.wiener@arm.com for c in simNode._children: 1148999Suri.wiener@arm.com child = simNode._children[c] 1158999Suri.wiener@arm.com if isSimObjectVector(child): 1168999Suri.wiener@arm.com for obj in child: 1178999Suri.wiener@arm.com dot_create_edges(obj, callgraph) 1188999Suri.wiener@arm.com else: 1198999Suri.wiener@arm.com dot_create_edges(child, callgraph) 1208999Suri.wiener@arm.com 1218999Suri.wiener@arm.comdef dot_add_edge(simNode, callgraph, full_port_name, peerPort): 1228999Suri.wiener@arm.com if peerPort.role == "MASTER": 1238999Suri.wiener@arm.com peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \ 1248999Suri.wiener@arm.com + "." + peerPort.peer.name) 1258999Suri.wiener@arm.com callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name)) 1268999Suri.wiener@arm.com 1278999Suri.wiener@arm.comdef dot_create_cluster(simNode, full_path, label): 1288999Suri.wiener@arm.com # if you read this, feel free to modify colors / style 1298999Suri.wiener@arm.com return pydot.Cluster( \ 1308999Suri.wiener@arm.com full_path, \ 1318999Suri.wiener@arm.com shape = "Mrecord", \ 1328999Suri.wiener@arm.com label = label, \ 1338999Suri.wiener@arm.com style = "\"rounded, filled\"", \ 1348999Suri.wiener@arm.com color = "#000000", \ 1358999Suri.wiener@arm.com fillcolor = dot_gen_color(simNode), \ 1368999Suri.wiener@arm.com fontname = "Arial", \ 1378999Suri.wiener@arm.com fontsize = "14", \ 1388999Suri.wiener@arm.com fontcolor = "#000000" \ 1398999Suri.wiener@arm.com ) 1408999Suri.wiener@arm.com 1418999Suri.wiener@arm.comdef dot_create_node(simNode, full_path, label): 1428999Suri.wiener@arm.com # if you read this, feel free to modify colors / style. 1438999Suri.wiener@arm.com # leafs may have a different style => seperate function 1448999Suri.wiener@arm.com return pydot.Node( \ 1458999Suri.wiener@arm.com full_path, \ 1468999Suri.wiener@arm.com shape = "Mrecord", \ 1478999Suri.wiener@arm.com label = label, \ 1488999Suri.wiener@arm.com style = "\"rounded, filled\"", \ 1498999Suri.wiener@arm.com color = "#000000", \ 1508999Suri.wiener@arm.com fillcolor = "#808080", \ 1518999Suri.wiener@arm.com fontname = "Arial", \ 1528999Suri.wiener@arm.com fontsize = "14", \ 1538999Suri.wiener@arm.com fontcolor = "#000000" \ 1548999Suri.wiener@arm.com ) 1558999Suri.wiener@arm.com 1568999Suri.wiener@arm.com# generate color for nodes 1578999Suri.wiener@arm.com# currently a simple grayscale. placeholder for aesthetic programmers. 1588999Suri.wiener@arm.comdef dot_gen_color(simNode): 1598999Suri.wiener@arm.com depth = len(simNode.path().split('.')) 1608999Suri.wiener@arm.com depth = 256 - depth * 16 * 3 1618999Suri.wiener@arm.com return dot_rgb_to_html(simNode, depth, depth, depth) 1628999Suri.wiener@arm.com 1638999Suri.wiener@arm.comdef dot_rgb_to_html(simNode, r, g, b): 1648999Suri.wiener@arm.com return "#%.2x%.2x%.2x" % (r, g, b) 1658999Suri.wiener@arm.com 1668999Suri.wiener@arm.comdef do_dot(root, outdir, dotFilename): 1678999Suri.wiener@arm.com if not pydot: 1688999Suri.wiener@arm.com return 1698999Suri.wiener@arm.com callgraph = pydot.Dot(graph_type='digraph') 1708999Suri.wiener@arm.com dot_create_nodes(root, callgraph) 1718999Suri.wiener@arm.com dot_create_edges(root, callgraph) 1728999Suri.wiener@arm.com dot_filename = os.path.join(outdir, dotFilename) 1738999Suri.wiener@arm.com callgraph.write(dot_filename) 1748999Suri.wiener@arm.com try: 1758999Suri.wiener@arm.com # dot crashes if the figure is extremely wide. 1768999Suri.wiener@arm.com # So avoid terminating simulation unnecessarily 1778999Suri.wiener@arm.com callgraph.write_pdf(dot_filename + ".pdf") 1788999Suri.wiener@arm.com except: 1798999Suri.wiener@arm.com print "warning: failed to generate pdf output from %s" % dot_filename 180