dot_writer.py revision 11418
19852Sandreas.hansson@arm.com# Copyright (c) 2012-2013 ARM Limited 28999Suri.wiener@arm.com# All rights reserved. 38999Suri.wiener@arm.com# 48999Suri.wiener@arm.com# The license below extends only to copyright in the software and shall 58999Suri.wiener@arm.com# not be construed as granting a license to any other intellectual 68999Suri.wiener@arm.com# property including but not limited to intellectual property relating 78999Suri.wiener@arm.com# to a hardware implementation of the functionality of the software 88999Suri.wiener@arm.com# licensed hereunder. You may use the software subject to the license 98999Suri.wiener@arm.com# terms below provided that you ensure that this notice is replicated 108999Suri.wiener@arm.com# unmodified and in its entirety in all distributions of the software, 118999Suri.wiener@arm.com# modified or unmodified, in source code or in binary form. 128999Suri.wiener@arm.com# 138999Suri.wiener@arm.com# Redistribution and use in source and binary forms, with or without 148999Suri.wiener@arm.com# modification, are permitted provided that the following conditions are 158999Suri.wiener@arm.com# met: redistributions of source code must retain the above copyright 168999Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer; 178999Suri.wiener@arm.com# redistributions in binary form must reproduce the above copyright 188999Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer in the 198999Suri.wiener@arm.com# documentation and/or other materials provided with the distribution; 208999Suri.wiener@arm.com# neither the name of the copyright holders nor the names of its 218999Suri.wiener@arm.com# contributors may be used to endorse or promote products derived from 228999Suri.wiener@arm.com# this software without specific prior written permission. 238999Suri.wiener@arm.com# 248999Suri.wiener@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 258999Suri.wiener@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 268999Suri.wiener@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 278999Suri.wiener@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 288999Suri.wiener@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 298999Suri.wiener@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 308999Suri.wiener@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 318999Suri.wiener@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 328999Suri.wiener@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 338999Suri.wiener@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 348999Suri.wiener@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 358999Suri.wiener@arm.com# 368999Suri.wiener@arm.com# Authors: Andreas Hansson 378999Suri.wiener@arm.com# Uri Wiener 3811418Ssascha.bischoff@arm.com# Sascha Bischoff 398999Suri.wiener@arm.com 408999Suri.wiener@arm.com##################################################################### 418999Suri.wiener@arm.com# 428999Suri.wiener@arm.com# System visualization using DOT 438999Suri.wiener@arm.com# 448999Suri.wiener@arm.com# While config.ini and config.json provide an almost complete listing 459852Sandreas.hansson@arm.com# of a system's components and connectivity, they lack a birds-eye 469852Sandreas.hansson@arm.com# view. The output generated by do_dot() is a DOT-based figure (as a 479852Sandreas.hansson@arm.com# pdf and an editable svg file) and its source dot code. Nodes are 489852Sandreas.hansson@arm.com# components, and edges represent the memory hierarchy: the edges are 499852Sandreas.hansson@arm.com# directed, from a master to slave. Initially all nodes are 509852Sandreas.hansson@arm.com# generated, and then all edges are added. do_dot should be called 519852Sandreas.hansson@arm.com# with the top-most SimObject (namely root but not necessarily), the 529852Sandreas.hansson@arm.com# output folder and the output dot source filename. From the given 539852Sandreas.hansson@arm.com# node, both processes (node and edge creation) is performed 549852Sandreas.hansson@arm.com# recursivly, traversing all children of the given root. 558999Suri.wiener@arm.com# 568999Suri.wiener@arm.com# pydot is required. When missing, no output will be generated. 578999Suri.wiener@arm.com# 588999Suri.wiener@arm.com##################################################################### 598999Suri.wiener@arm.com 608999Suri.wiener@arm.comimport m5, os, re 618999Suri.wiener@arm.comfrom m5.SimObject import isRoot, isSimObjectVector 6210176Ssascha.bischoff@arm.comfrom m5.params import PortRef 639528Ssascha.bischoff@arm.comfrom m5.util import warn 648999Suri.wiener@arm.comtry: 658999Suri.wiener@arm.com import pydot 668999Suri.wiener@arm.comexcept: 678999Suri.wiener@arm.com pydot = False 688999Suri.wiener@arm.com 698999Suri.wiener@arm.com# need to create all nodes (components) before creating edges (memory channels) 708999Suri.wiener@arm.comdef dot_create_nodes(simNode, callgraph): 718999Suri.wiener@arm.com if isRoot(simNode): 728999Suri.wiener@arm.com label = "root" 738999Suri.wiener@arm.com else: 748999Suri.wiener@arm.com label = simNode._name 758999Suri.wiener@arm.com full_path = re.sub('\.', '_', simNode.path()) 769852Sandreas.hansson@arm.com # add class name under the label 779852Sandreas.hansson@arm.com label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 788999Suri.wiener@arm.com 798999Suri.wiener@arm.com # each component is a sub-graph (cluster) 808999Suri.wiener@arm.com cluster = dot_create_cluster(simNode, full_path, label) 818999Suri.wiener@arm.com 828999Suri.wiener@arm.com # create nodes per port 838999Suri.wiener@arm.com for port_name in simNode._ports.keys(): 848999Suri.wiener@arm.com port = simNode._port_refs.get(port_name, None) 858999Suri.wiener@arm.com if port != None: 868999Suri.wiener@arm.com full_port_name = full_path + "_" + port_name 878999Suri.wiener@arm.com port_node = dot_create_node(simNode, full_port_name, port_name) 888999Suri.wiener@arm.com cluster.add_node(port_node) 898999Suri.wiener@arm.com 908999Suri.wiener@arm.com # recurse to children 918999Suri.wiener@arm.com if simNode._children: 928999Suri.wiener@arm.com for c in simNode._children: 938999Suri.wiener@arm.com child = simNode._children[c] 948999Suri.wiener@arm.com if isSimObjectVector(child): 958999Suri.wiener@arm.com for obj in child: 968999Suri.wiener@arm.com dot_create_nodes(obj, cluster) 978999Suri.wiener@arm.com else: 988999Suri.wiener@arm.com dot_create_nodes(child, cluster) 998999Suri.wiener@arm.com 1008999Suri.wiener@arm.com callgraph.add_subgraph(cluster) 1018999Suri.wiener@arm.com 1028999Suri.wiener@arm.com# create all edges according to memory hierarchy 1038999Suri.wiener@arm.comdef dot_create_edges(simNode, callgraph): 1048999Suri.wiener@arm.com for port_name in simNode._ports.keys(): 1058999Suri.wiener@arm.com port = simNode._port_refs.get(port_name, None) 1068999Suri.wiener@arm.com if port != None: 1078999Suri.wiener@arm.com full_path = re.sub('\.', '_', simNode.path()) 1088999Suri.wiener@arm.com full_port_name = full_path + "_" + port_name 1098999Suri.wiener@arm.com port_node = dot_create_node(simNode, full_port_name, port_name) 1108999Suri.wiener@arm.com # create edges 11110176Ssascha.bischoff@arm.com if isinstance(port, PortRef): 1128999Suri.wiener@arm.com dot_add_edge(simNode, callgraph, full_port_name, port) 1138999Suri.wiener@arm.com else: 1148999Suri.wiener@arm.com for p in port.elements: 1158999Suri.wiener@arm.com dot_add_edge(simNode, callgraph, full_port_name, p) 1168999Suri.wiener@arm.com 1178999Suri.wiener@arm.com # recurse to children 1188999Suri.wiener@arm.com if simNode._children: 1198999Suri.wiener@arm.com for c in simNode._children: 1208999Suri.wiener@arm.com child = simNode._children[c] 1218999Suri.wiener@arm.com if isSimObjectVector(child): 1228999Suri.wiener@arm.com for obj in child: 1238999Suri.wiener@arm.com dot_create_edges(obj, callgraph) 1248999Suri.wiener@arm.com else: 1258999Suri.wiener@arm.com dot_create_edges(child, callgraph) 1268999Suri.wiener@arm.com 1278999Suri.wiener@arm.comdef dot_add_edge(simNode, callgraph, full_port_name, peerPort): 1288999Suri.wiener@arm.com if peerPort.role == "MASTER": 1298999Suri.wiener@arm.com peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \ 1308999Suri.wiener@arm.com + "." + peerPort.peer.name) 1318999Suri.wiener@arm.com callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name)) 1328999Suri.wiener@arm.com 1338999Suri.wiener@arm.comdef dot_create_cluster(simNode, full_path, label): 1349854Sandreas.hansson@arm.com # get the parameter values of the node and use them as a tooltip 1359854Sandreas.hansson@arm.com ini_strings = [] 1369854Sandreas.hansson@arm.com for param in sorted(simNode._params.keys()): 1379854Sandreas.hansson@arm.com value = simNode._values.get(param) 1389854Sandreas.hansson@arm.com if value != None: 1399854Sandreas.hansson@arm.com # parameter name = value in HTML friendly format 1409854Sandreas.hansson@arm.com ini_strings.append(str(param) + "=" + 1419854Sandreas.hansson@arm.com simNode._values[param].ini_str()) 1429854Sandreas.hansson@arm.com # join all the parameters with an HTML newline 1439854Sandreas.hansson@arm.com tooltip = " ".join(ini_strings) 1449854Sandreas.hansson@arm.com 1458999Suri.wiener@arm.com return pydot.Cluster( \ 1468999Suri.wiener@arm.com full_path, \ 1478999Suri.wiener@arm.com shape = "Mrecord", \ 1488999Suri.wiener@arm.com label = label, \ 1499854Sandreas.hansson@arm.com tooltip = "\"" + tooltip + "\"", \ 1508999Suri.wiener@arm.com style = "\"rounded, filled\"", \ 1518999Suri.wiener@arm.com color = "#000000", \ 1529853Sandreas.hansson@arm.com fillcolor = dot_gen_colour(simNode), \ 1538999Suri.wiener@arm.com fontname = "Arial", \ 1548999Suri.wiener@arm.com fontsize = "14", \ 1558999Suri.wiener@arm.com fontcolor = "#000000" \ 1568999Suri.wiener@arm.com ) 1578999Suri.wiener@arm.com 1588999Suri.wiener@arm.comdef dot_create_node(simNode, full_path, label): 1598999Suri.wiener@arm.com return pydot.Node( \ 1608999Suri.wiener@arm.com full_path, \ 1618999Suri.wiener@arm.com shape = "Mrecord", \ 1628999Suri.wiener@arm.com label = label, \ 1638999Suri.wiener@arm.com style = "\"rounded, filled\"", \ 1648999Suri.wiener@arm.com color = "#000000", \ 1659853Sandreas.hansson@arm.com fillcolor = dot_gen_colour(simNode, True), \ 1668999Suri.wiener@arm.com fontname = "Arial", \ 1678999Suri.wiener@arm.com fontsize = "14", \ 1688999Suri.wiener@arm.com fontcolor = "#000000" \ 1698999Suri.wiener@arm.com ) 1708999Suri.wiener@arm.com 1719853Sandreas.hansson@arm.com# an enumerator for different kinds of node types, at the moment we 1729853Sandreas.hansson@arm.com# discern the majority of node types, with the caches being the 1739853Sandreas.hansson@arm.com# notable exception 1749853Sandreas.hansson@arm.comclass NodeType: 1759853Sandreas.hansson@arm.com SYS = 0 1769853Sandreas.hansson@arm.com CPU = 1 17710405Sandreas.hansson@arm.com XBAR = 2 1789853Sandreas.hansson@arm.com MEM = 3 1799853Sandreas.hansson@arm.com DEV = 4 1809853Sandreas.hansson@arm.com OTHER = 5 1819853Sandreas.hansson@arm.com 1829853Sandreas.hansson@arm.com# based on the sim object, determine the node type 1839853Sandreas.hansson@arm.comdef get_node_type(simNode): 1849853Sandreas.hansson@arm.com if isinstance(simNode, m5.objects.System): 1859853Sandreas.hansson@arm.com return NodeType.SYS 1869853Sandreas.hansson@arm.com # NULL ISA has no BaseCPU or PioDevice, so check if these names 1879853Sandreas.hansson@arm.com # exists before using them 1889853Sandreas.hansson@arm.com elif 'BaseCPU' in dir(m5.objects) and \ 1899853Sandreas.hansson@arm.com isinstance(simNode, m5.objects.BaseCPU): 1909853Sandreas.hansson@arm.com return NodeType.CPU 1919853Sandreas.hansson@arm.com elif 'PioDevice' in dir(m5.objects) and \ 1929853Sandreas.hansson@arm.com isinstance(simNode, m5.objects.PioDevice): 1939853Sandreas.hansson@arm.com return NodeType.DEV 19410405Sandreas.hansson@arm.com elif isinstance(simNode, m5.objects.BaseXBar): 19510405Sandreas.hansson@arm.com return NodeType.XBAR 1969853Sandreas.hansson@arm.com elif isinstance(simNode, m5.objects.AbstractMemory): 1979853Sandreas.hansson@arm.com return NodeType.MEM 1989853Sandreas.hansson@arm.com else: 1999853Sandreas.hansson@arm.com return NodeType.OTHER 2009853Sandreas.hansson@arm.com 2019853Sandreas.hansson@arm.com# based on the node type, determine the colour as an RGB tuple, the 2029853Sandreas.hansson@arm.com# palette is rather arbitrary at this point (some coherent natural 2039853Sandreas.hansson@arm.com# tones), and someone that feels artistic should probably have a look 2049853Sandreas.hansson@arm.comdef get_type_colour(nodeType): 2059853Sandreas.hansson@arm.com if nodeType == NodeType.SYS: 2069853Sandreas.hansson@arm.com return (228, 231, 235) 2079853Sandreas.hansson@arm.com elif nodeType == NodeType.CPU: 2089853Sandreas.hansson@arm.com return (187, 198, 217) 20910405Sandreas.hansson@arm.com elif nodeType == NodeType.XBAR: 2109853Sandreas.hansson@arm.com return (111, 121, 140) 2119853Sandreas.hansson@arm.com elif nodeType == NodeType.MEM: 2129853Sandreas.hansson@arm.com return (94, 89, 88) 2139853Sandreas.hansson@arm.com elif nodeType == NodeType.DEV: 2149853Sandreas.hansson@arm.com return (199, 167, 147) 2159853Sandreas.hansson@arm.com elif nodeType == NodeType.OTHER: 2169853Sandreas.hansson@arm.com # use a relatively gray shade 2179853Sandreas.hansson@arm.com return (186, 182, 174) 2189853Sandreas.hansson@arm.com 2199853Sandreas.hansson@arm.com# generate colour for a node, either corresponding to a sim object or a 2209853Sandreas.hansson@arm.com# port 2219853Sandreas.hansson@arm.comdef dot_gen_colour(simNode, isPort = False): 2229853Sandreas.hansson@arm.com # determine the type of the current node, and also its parent, if 2239853Sandreas.hansson@arm.com # the node is not the same type as the parent then we use the base 2249853Sandreas.hansson@arm.com # colour for its type 2259853Sandreas.hansson@arm.com node_type = get_node_type(simNode) 2269853Sandreas.hansson@arm.com if simNode._parent: 2279853Sandreas.hansson@arm.com parent_type = get_node_type(simNode._parent) 2289853Sandreas.hansson@arm.com else: 2299853Sandreas.hansson@arm.com parent_type = NodeType.OTHER 2309853Sandreas.hansson@arm.com 2319853Sandreas.hansson@arm.com # if this node is the same type as the parent, then scale the 2329853Sandreas.hansson@arm.com # colour based on the depth such that the deeper levels in the 2339853Sandreas.hansson@arm.com # hierarchy get darker colours 2349853Sandreas.hansson@arm.com if node_type == parent_type: 2359853Sandreas.hansson@arm.com # start out with a depth of zero 2369853Sandreas.hansson@arm.com depth = 0 2379853Sandreas.hansson@arm.com parent = simNode._parent 2389853Sandreas.hansson@arm.com # find the closes parent that is not the same type 2399853Sandreas.hansson@arm.com while parent and get_node_type(parent) == parent_type: 2409853Sandreas.hansson@arm.com depth = depth + 1 2419853Sandreas.hansson@arm.com parent = parent._parent 2429853Sandreas.hansson@arm.com node_colour = get_type_colour(parent_type) 2439853Sandreas.hansson@arm.com # slightly arbitrary, but assume that the depth is less than 2449853Sandreas.hansson@arm.com # five levels 2459853Sandreas.hansson@arm.com r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour) 2469853Sandreas.hansson@arm.com else: 2479853Sandreas.hansson@arm.com node_colour = get_type_colour(node_type) 2489853Sandreas.hansson@arm.com r, g, b = node_colour 2499853Sandreas.hansson@arm.com 2509853Sandreas.hansson@arm.com # if we are colouring a port, then make it a slightly darker shade 2519853Sandreas.hansson@arm.com # than the node that encapsulates it, once again use a magic constant 2529853Sandreas.hansson@arm.com if isPort: 2539853Sandreas.hansson@arm.com r, g, b = map(lambda x: 0.8 * x, (r, g, b)) 2548999Suri.wiener@arm.com 2559852Sandreas.hansson@arm.com return dot_rgb_to_html(r, g, b) 2569852Sandreas.hansson@arm.com 2579852Sandreas.hansson@arm.comdef dot_rgb_to_html(r, g, b): 2588999Suri.wiener@arm.com return "#%.2x%.2x%.2x" % (r, g, b) 2598999Suri.wiener@arm.com 26011418Ssascha.bischoff@arm.com# We need to create all of the clock domains. We abuse the alpha channel to get 26111418Ssascha.bischoff@arm.com# the correct domain colouring. 26211418Ssascha.bischoff@arm.comdef dot_add_clk_domain(c_dom, v_dom): 26311418Ssascha.bischoff@arm.com label = "\"" + str(c_dom) + "\ :\ " + str(v_dom) + "\"" 26411418Ssascha.bischoff@arm.com label = re.sub('\.', '_', str(label)) 26511418Ssascha.bischoff@arm.com full_path = re.sub('\.', '_', str(c_dom)) 26611418Ssascha.bischoff@arm.com return pydot.Cluster( \ 26711418Ssascha.bischoff@arm.com full_path, \ 26811418Ssascha.bischoff@arm.com shape = "Mrecord", \ 26911418Ssascha.bischoff@arm.com label = label, \ 27011418Ssascha.bischoff@arm.com style = "\"rounded, filled, dashed\"", \ 27111418Ssascha.bischoff@arm.com color = "#000000", \ 27211418Ssascha.bischoff@arm.com fillcolor = "#AFC8AF8F", \ 27311418Ssascha.bischoff@arm.com fontname = "Arial", \ 27411418Ssascha.bischoff@arm.com fontsize = "14", \ 27511418Ssascha.bischoff@arm.com fontcolor = "#000000" \ 27611418Ssascha.bischoff@arm.com ) 27711418Ssascha.bischoff@arm.com 27811418Ssascha.bischoff@arm.comdef dot_create_dvfs_nodes(simNode, callgraph, domain=None): 27911418Ssascha.bischoff@arm.com if isRoot(simNode): 28011418Ssascha.bischoff@arm.com label = "root" 28111418Ssascha.bischoff@arm.com else: 28211418Ssascha.bischoff@arm.com label = simNode._name 28311418Ssascha.bischoff@arm.com full_path = re.sub('\.', '_', simNode.path()) 28411418Ssascha.bischoff@arm.com # add class name under the label 28511418Ssascha.bischoff@arm.com label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 28611418Ssascha.bischoff@arm.com 28711418Ssascha.bischoff@arm.com # each component is a sub-graph (cluster) 28811418Ssascha.bischoff@arm.com cluster = dot_create_cluster(simNode, full_path, label) 28911418Ssascha.bischoff@arm.com 29011418Ssascha.bischoff@arm.com # create nodes per port 29111418Ssascha.bischoff@arm.com for port_name in simNode._ports.keys(): 29211418Ssascha.bischoff@arm.com port = simNode._port_refs.get(port_name, None) 29311418Ssascha.bischoff@arm.com if port != None: 29411418Ssascha.bischoff@arm.com full_port_name = full_path + "_" + port_name 29511418Ssascha.bischoff@arm.com port_node = dot_create_node(simNode, full_port_name, port_name) 29611418Ssascha.bischoff@arm.com cluster.add_node(port_node) 29711418Ssascha.bischoff@arm.com 29811418Ssascha.bischoff@arm.com # Dictionary of DVFS domains 29911418Ssascha.bischoff@arm.com dvfs_domains = {} 30011418Ssascha.bischoff@arm.com 30111418Ssascha.bischoff@arm.com # recurse to children 30211418Ssascha.bischoff@arm.com if simNode._children: 30311418Ssascha.bischoff@arm.com for c in simNode._children: 30411418Ssascha.bischoff@arm.com child = simNode._children[c] 30511418Ssascha.bischoff@arm.com if isSimObjectVector(child): 30611418Ssascha.bischoff@arm.com for obj in child: 30711418Ssascha.bischoff@arm.com try: 30811418Ssascha.bischoff@arm.com c_dom = obj.__getattr__('clk_domain') 30911418Ssascha.bischoff@arm.com v_dom = c_dom.__getattr__('voltage_domain') 31011418Ssascha.bischoff@arm.com except AttributeError: 31111418Ssascha.bischoff@arm.com # Just re-use the domain from above 31211418Ssascha.bischoff@arm.com c_dom = domain 31311418Ssascha.bischoff@arm.com c_dom.__getattr__('voltage_domain') 31411418Ssascha.bischoff@arm.com pass 31511418Ssascha.bischoff@arm.com 31611418Ssascha.bischoff@arm.com if c_dom == domain or c_dom == None: 31711418Ssascha.bischoff@arm.com dot_create_dvfs_nodes(obj, cluster, domain) 31811418Ssascha.bischoff@arm.com else: 31911418Ssascha.bischoff@arm.com if c_dom not in dvfs_domains: 32011418Ssascha.bischoff@arm.com dvfs_cluster = dot_add_clk_domain(c_dom, v_dom) 32111418Ssascha.bischoff@arm.com dvfs_domains[c_dom] = dvfs_cluster 32211418Ssascha.bischoff@arm.com else: 32311418Ssascha.bischoff@arm.com dvfs_cluster = dvfs_domains[c_dom] 32411418Ssascha.bischoff@arm.com dot_create_dvfs_nodes(obj, dvfs_cluster, c_dom) 32511418Ssascha.bischoff@arm.com else: 32611418Ssascha.bischoff@arm.com try: 32711418Ssascha.bischoff@arm.com c_dom = child.__getattr__('clk_domain') 32811418Ssascha.bischoff@arm.com v_dom = c_dom.__getattr__('voltage_domain') 32911418Ssascha.bischoff@arm.com except AttributeError: 33011418Ssascha.bischoff@arm.com # Just re-use the domain from above 33111418Ssascha.bischoff@arm.com c_dom = domain 33211418Ssascha.bischoff@arm.com c_dom.__getattr__('voltage_domain') 33311418Ssascha.bischoff@arm.com pass 33411418Ssascha.bischoff@arm.com 33511418Ssascha.bischoff@arm.com if c_dom == domain or c_dom == None: 33611418Ssascha.bischoff@arm.com dot_create_dvfs_nodes(child, cluster, domain) 33711418Ssascha.bischoff@arm.com else: 33811418Ssascha.bischoff@arm.com if c_dom not in dvfs_domains: 33911418Ssascha.bischoff@arm.com dvfs_cluster = dot_add_clk_domain(c_dom, v_dom) 34011418Ssascha.bischoff@arm.com dvfs_domains[c_dom] = dvfs_cluster 34111418Ssascha.bischoff@arm.com else: 34211418Ssascha.bischoff@arm.com dvfs_cluster = dvfs_domains[c_dom] 34311418Ssascha.bischoff@arm.com dot_create_dvfs_nodes(child, dvfs_cluster, c_dom) 34411418Ssascha.bischoff@arm.com 34511418Ssascha.bischoff@arm.com for key in dvfs_domains: 34611418Ssascha.bischoff@arm.com cluster.add_subgraph(dvfs_domains[key]) 34711418Ssascha.bischoff@arm.com 34811418Ssascha.bischoff@arm.com callgraph.add_subgraph(cluster) 34911418Ssascha.bischoff@arm.com 3508999Suri.wiener@arm.comdef do_dot(root, outdir, dotFilename): 3518999Suri.wiener@arm.com if not pydot: 3528999Suri.wiener@arm.com return 3539852Sandreas.hansson@arm.com # * use ranksep > 1.0 for for vertical separation between nodes 3549852Sandreas.hansson@arm.com # especially useful if you need to annotate edges using e.g. visio 3559852Sandreas.hansson@arm.com # which accepts svg format 3569852Sandreas.hansson@arm.com # * no need for hoizontal separation as nothing moves horizonally 3579852Sandreas.hansson@arm.com callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 3588999Suri.wiener@arm.com dot_create_nodes(root, callgraph) 3598999Suri.wiener@arm.com dot_create_edges(root, callgraph) 3608999Suri.wiener@arm.com dot_filename = os.path.join(outdir, dotFilename) 3618999Suri.wiener@arm.com callgraph.write(dot_filename) 3628999Suri.wiener@arm.com try: 3638999Suri.wiener@arm.com # dot crashes if the figure is extremely wide. 3648999Suri.wiener@arm.com # So avoid terminating simulation unnecessarily 3659852Sandreas.hansson@arm.com callgraph.write_svg(dot_filename + ".svg") 3668999Suri.wiener@arm.com callgraph.write_pdf(dot_filename + ".pdf") 3678999Suri.wiener@arm.com except: 3689853Sandreas.hansson@arm.com warn("failed to generate dot output from %s", dot_filename) 36911418Ssascha.bischoff@arm.com 37011418Ssascha.bischoff@arm.comdef do_dvfs_dot(root, outdir, dotFilename): 37111418Ssascha.bischoff@arm.com if not pydot: 37211418Ssascha.bischoff@arm.com return 37311418Ssascha.bischoff@arm.com dvfsgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 37411418Ssascha.bischoff@arm.com dot_create_dvfs_nodes(root, dvfsgraph) 37511418Ssascha.bischoff@arm.com dot_create_edges(root, dvfsgraph) 37611418Ssascha.bischoff@arm.com dot_filename = os.path.join(outdir, dotFilename) 37711418Ssascha.bischoff@arm.com dvfsgraph.write(dot_filename) 37811418Ssascha.bischoff@arm.com try: 37911418Ssascha.bischoff@arm.com # dot crashes if the figure is extremely wide. 38011418Ssascha.bischoff@arm.com # So avoid terminating simulation unnecessarily 38111418Ssascha.bischoff@arm.com dvfsgraph.write_svg(dot_filename + ".svg") 38211418Ssascha.bischoff@arm.com dvfsgraph.write_pdf(dot_filename + ".pdf") 38311418Ssascha.bischoff@arm.com except: 38411418Ssascha.bischoff@arm.com warn("failed to generate dot output from %s", dot_filename) 385