simulate.py revision 12011
18999Suri.wiener@arm.com# Copyright (c) 2012 ARM Limited 28999Suri.wiener@arm.com# All rights reserved. 38999Suri.wiener@arm.com# 48999Suri.wiener@arm.com# The license below extends only to copyright in the software and shall 58999Suri.wiener@arm.com# not be construed as granting a license to any other intellectual 68999Suri.wiener@arm.com# property including but not limited to intellectual property relating 78999Suri.wiener@arm.com# to a hardware implementation of the functionality of the software 88999Suri.wiener@arm.com# licensed hereunder. You may use the software subject to the license 98999Suri.wiener@arm.com# terms below provided that you ensure that this notice is replicated 108999Suri.wiener@arm.com# unmodified and in its entirety in all distributions of the software, 118999Suri.wiener@arm.com# modified or unmodified, in source code or in binary form. 128999Suri.wiener@arm.com# 134762Snate@binkert.org# Copyright (c) 2005 The Regents of The University of Michigan 147534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 154762Snate@binkert.org# All rights reserved. 164762Snate@binkert.org# 174762Snate@binkert.org# Redistribution and use in source and binary forms, with or without 184762Snate@binkert.org# modification, are permitted provided that the following conditions are 194762Snate@binkert.org# met: redistributions of source code must retain the above copyright 204762Snate@binkert.org# notice, this list of conditions and the following disclaimer; 214762Snate@binkert.org# redistributions in binary form must reproduce the above copyright 224762Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 234762Snate@binkert.org# documentation and/or other materials provided with the distribution; 244762Snate@binkert.org# neither the name of the copyright holders nor the names of its 254762Snate@binkert.org# contributors may be used to endorse or promote products derived from 264762Snate@binkert.org# this software without specific prior written permission. 274762Snate@binkert.org# 284762Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294762Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304762Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314762Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324762Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334762Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344762Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354762Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364762Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374762Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384762Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394762Snate@binkert.org# 404762Snate@binkert.org# Authors: Nathan Binkert 414762Snate@binkert.org# Steve Reinhardt 424762Snate@binkert.org 434762Snate@binkert.orgimport atexit 444762Snate@binkert.orgimport os 454762Snate@binkert.orgimport sys 464762Snate@binkert.org 4711991Sandreas.sandberg@arm.com# import the wrapped C++ functions 4811802Sandreas.sandberg@arm.comimport _m5.drain 4911802Sandreas.sandberg@arm.comimport _m5.core 5011802Sandreas.sandberg@arm.comfrom _m5.stats import updateEvents as updateStatEvents 5111802Sandreas.sandberg@arm.com 526001Snate@binkert.orgimport stats 534762Snate@binkert.orgimport SimObject 544762Snate@binkert.orgimport ticks 554851Snate@binkert.orgimport objects 5611418Ssascha.bischoff@arm.comfrom m5.util.dot_writer import do_dot, do_dvfs_dot 578999Suri.wiener@arm.com 587525Ssteve.reinhardt@amd.comfrom util import fatal 598664SAli.Saidi@ARM.comfrom util import attrdict 604762Snate@binkert.org 619811Sandreas.hansson@arm.com# define a MaxTick parameter, unsigned 64 bit 629811Sandreas.hansson@arm.comMaxTick = 2**64 - 1 636654Snate@binkert.org 649521SAndreas.Sandberg@ARM.com_memory_modes = { 659521SAndreas.Sandberg@ARM.com "atomic" : objects.params.atomic, 669521SAndreas.Sandberg@ARM.com "timing" : objects.params.timing, 679524SAndreas.Sandberg@ARM.com "atomic_noncaching" : objects.params.atomic_noncaching, 689521SAndreas.Sandberg@ARM.com } 699521SAndreas.Sandberg@ARM.com 7011802Sandreas.sandberg@arm.com_drain_manager = _m5.drain.DrainManager.instance() 7110912Sandreas.sandberg@arm.com 724762Snate@binkert.org# The final hook to generate .ini files. Called from the user script 734762Snate@binkert.org# once the config is built. 747531Ssteve.reinhardt@amd.comdef instantiate(ckpt_dir=None): 758245Snate@binkert.org from m5 import options 768234Snate@binkert.org 777525Ssteve.reinhardt@amd.com root = objects.Root.getInstance() 787525Ssteve.reinhardt@amd.com 797525Ssteve.reinhardt@amd.com if not root: 807525Ssteve.reinhardt@amd.com fatal("Need to instantiate Root() before calling instantiate()") 817525Ssteve.reinhardt@amd.com 824762Snate@binkert.org # we need to fix the global frequency 834762Snate@binkert.org ticks.fixGlobalFrequency() 844762Snate@binkert.org 857528Ssteve.reinhardt@amd.com # Make sure SimObject-valued params are in the configuration 867528Ssteve.reinhardt@amd.com # hierarchy so we catch them with future descendants() walks 877528Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.adoptOrphanParams() 887528Ssteve.reinhardt@amd.com 897527Ssteve.reinhardt@amd.com # Unproxy in sorted order for determinism 907527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.unproxyParams() 915037Smilesck@eecs.umich.edu 925773Snate@binkert.org if options.dump_config: 935773Snate@binkert.org ini_file = file(os.path.join(options.outdir, options.dump_config), 'w') 947527Ssteve.reinhardt@amd.com # Print ini sections in sorted order for easier diffing 957527Ssteve.reinhardt@amd.com for obj in sorted(root.descendants(), key=lambda o: o.path()): 967527Ssteve.reinhardt@amd.com obj.print_ini(ini_file) 975773Snate@binkert.org ini_file.close() 984762Snate@binkert.org 998664SAli.Saidi@ARM.com if options.json_config: 1008675SAli.Saidi@ARM.com try: 1018675SAli.Saidi@ARM.com import json 1028675SAli.Saidi@ARM.com json_file = file(os.path.join(options.outdir, options.json_config), 'w') 1038675SAli.Saidi@ARM.com d = root.get_config_as_dict() 1048675SAli.Saidi@ARM.com json.dump(d, json_file, indent=4) 1058675SAli.Saidi@ARM.com json_file.close() 1068675SAli.Saidi@ARM.com except ImportError: 1078675SAli.Saidi@ARM.com pass 1088664SAli.Saidi@ARM.com 1098999Suri.wiener@arm.com do_dot(root, options.outdir, options.dot_config) 1108664SAli.Saidi@ARM.com 1114762Snate@binkert.org # Initialize the global statistics 1126001Snate@binkert.org stats.initSimStats() 1134762Snate@binkert.org 1144762Snate@binkert.org # Create the C++ sim objects and connect ports 1157527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.createCCObject() 1167527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.connectPorts() 1174762Snate@binkert.org 1184762Snate@binkert.org # Do a second pass to finish initializing the sim objects 1197527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.init() 1204762Snate@binkert.org 1214762Snate@binkert.org # Do a third pass to initialize statistics 1227527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.regStats() 1234762Snate@binkert.org 12410023Smatt.horsnell@ARM.com # Do a fourth pass to initialize probe points 12510023Smatt.horsnell@ARM.com for obj in root.descendants(): obj.regProbePoints() 12610023Smatt.horsnell@ARM.com 12710023Smatt.horsnell@ARM.com # Do a fifth pass to connect probe listeners 12810023Smatt.horsnell@ARM.com for obj in root.descendants(): obj.regProbeListeners() 12910023Smatt.horsnell@ARM.com 13011418Ssascha.bischoff@arm.com # We want to generate the DVFS diagram for the system. This can only be 13111418Ssascha.bischoff@arm.com # done once all of the CPP objects have been created and initialised so 13211418Ssascha.bischoff@arm.com # that we are able to figure out which object belongs to which domain. 13311431Ssascha.bischoff@arm.com if options.dot_dvfs_config: 13411431Ssascha.bischoff@arm.com do_dvfs_dot(root, options.outdir, options.dot_dvfs_config) 13511418Ssascha.bischoff@arm.com 1366001Snate@binkert.org # We're done registering statistics. Enable the stats package now. 1376001Snate@binkert.org stats.enable() 1384762Snate@binkert.org 1397531Ssteve.reinhardt@amd.com # Restore checkpoint (if any) 1407531Ssteve.reinhardt@amd.com if ckpt_dir: 14110912Sandreas.sandberg@arm.com _drain_manager.preCheckpointRestore() 14211802Sandreas.sandberg@arm.com ckpt = _m5.core.getCheckpoint(ckpt_dir) 14311802Sandreas.sandberg@arm.com _m5.core.unserializeGlobals(ckpt); 1447532Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.loadState(ckpt) 1457532Ssteve.reinhardt@amd.com else: 1467532Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.initState() 1477531Ssteve.reinhardt@amd.com 1489262Ssascha.bischoff@arm.com # Check to see if any of the stat events are in the past after resuming from 1499262Ssascha.bischoff@arm.com # a checkpoint, If so, this call will shift them to be at a valid time. 1509262Ssascha.bischoff@arm.com updateStatEvents() 1519262Ssascha.bischoff@arm.com 1524762Snate@binkert.orgneed_startup = True 1534762Snate@binkert.orgdef simulate(*args, **kwargs): 15410912Sandreas.sandberg@arm.com global need_startup 1554762Snate@binkert.org 1564762Snate@binkert.org if need_startup: 1577527Ssteve.reinhardt@amd.com root = objects.Root.getInstance() 1587527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.startup() 1594762Snate@binkert.org need_startup = False 1604762Snate@binkert.org 1619983Sstever@gmail.com # Python exit handlers happen in reverse order. 1629983Sstever@gmail.com # We want to dump stats last. 1639983Sstever@gmail.com atexit.register(stats.dump) 1649983Sstever@gmail.com 1659983Sstever@gmail.com # register our C++ exit callback function with Python 16611802Sandreas.sandberg@arm.com atexit.register(_m5.core.doExitCleanup) 1679983Sstever@gmail.com 1689993Snilay@cs.wisc.edu # Reset to put the stats in a consistent state. 1699993Snilay@cs.wisc.edu stats.reset() 1709993Snilay@cs.wisc.edu 17110912Sandreas.sandberg@arm.com if _drain_manager.isDrained(): 17210912Sandreas.sandberg@arm.com _drain_manager.resume() 1734762Snate@binkert.org 17411802Sandreas.sandberg@arm.com return _m5.event.simulate(*args, **kwargs) 1754762Snate@binkert.org 17610912Sandreas.sandberg@arm.comdef drain(): 17710912Sandreas.sandberg@arm.com """Drain the simulator in preparation of a checkpoint or memory mode 17810912Sandreas.sandberg@arm.com switch. 17910912Sandreas.sandberg@arm.com 18010912Sandreas.sandberg@arm.com This operation is a no-op if the simulator is already in the 18110912Sandreas.sandberg@arm.com Drained state. 18210912Sandreas.sandberg@arm.com 18310912Sandreas.sandberg@arm.com """ 18410912Sandreas.sandberg@arm.com 1859344SAndreas.Sandberg@arm.com # Try to drain all objects. Draining might not be completed unless 1869344SAndreas.Sandberg@arm.com # all objects return that they are drained on the first call. This 1879344SAndreas.Sandberg@arm.com # is because as objects drain they may cause other objects to no 1889344SAndreas.Sandberg@arm.com # longer be drained. 1899344SAndreas.Sandberg@arm.com def _drain(): 19010912Sandreas.sandberg@arm.com # Try to drain the system. The drain is successful if all 19110912Sandreas.sandberg@arm.com # objects are done without simulation. We need to simulate 19210912Sandreas.sandberg@arm.com # more if not. 19310912Sandreas.sandberg@arm.com if _drain_manager.tryDrain(): 19410912Sandreas.sandberg@arm.com return True 19510912Sandreas.sandberg@arm.com 19610912Sandreas.sandberg@arm.com # WARNING: if a valid exit event occurs while draining, it 19710912Sandreas.sandberg@arm.com # will not get returned to the user script 19811802Sandreas.sandberg@arm.com exit_event = _m5.event.simulate() 19910912Sandreas.sandberg@arm.com while exit_event.getCause() != 'Finished drain': 20010436Slukefahr@umich.edu exit_event = simulate() 2019344SAndreas.Sandberg@arm.com 20210912Sandreas.sandberg@arm.com return False 20310912Sandreas.sandberg@arm.com 20410912Sandreas.sandberg@arm.com # Don't try to drain a system that is already drained 20510912Sandreas.sandberg@arm.com is_drained = _drain_manager.isDrained() 20610912Sandreas.sandberg@arm.com while not is_drained: 20710912Sandreas.sandberg@arm.com is_drained = _drain() 20810912Sandreas.sandberg@arm.com 20910912Sandreas.sandberg@arm.com assert _drain_manager.isDrained(), "Drain state inconsistent" 2104762Snate@binkert.org 2119346SAndreas.Sandberg@arm.comdef memWriteback(root): 2129346SAndreas.Sandberg@arm.com for obj in root.descendants(): 2139346SAndreas.Sandberg@arm.com obj.memWriteback() 2149346SAndreas.Sandberg@arm.com 2159346SAndreas.Sandberg@arm.comdef memInvalidate(root): 2169346SAndreas.Sandberg@arm.com for obj in root.descendants(): 2179346SAndreas.Sandberg@arm.com obj.memInvalidate() 2189346SAndreas.Sandberg@arm.com 2197525Ssteve.reinhardt@amd.comdef checkpoint(dir): 2207525Ssteve.reinhardt@amd.com root = objects.Root.getInstance() 2214762Snate@binkert.org if not isinstance(root, objects.Root): 2224762Snate@binkert.org raise TypeError, "Checkpoint must be called on a root object." 22310912Sandreas.sandberg@arm.com 22410912Sandreas.sandberg@arm.com drain() 2259346SAndreas.Sandberg@arm.com memWriteback(root) 2264762Snate@binkert.org print "Writing checkpoint" 22711802Sandreas.sandberg@arm.com _m5.core.serializeAll(dir) 2284762Snate@binkert.org 2299521SAndreas.Sandberg@ARM.comdef _changeMemoryMode(system, mode): 2304762Snate@binkert.org if not isinstance(system, (objects.Root, objects.System)): 2314762Snate@binkert.org raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ 2324762Snate@binkert.org (type(system), objects.Root, objects.System) 2339343SAndreas.Sandberg@arm.com if system.getMemoryMode() != mode: 2349343SAndreas.Sandberg@arm.com system.setMemoryMode(mode) 2359343SAndreas.Sandberg@arm.com else: 2369343SAndreas.Sandberg@arm.com print "System already in target mode. Memory mode unchanged." 2374762Snate@binkert.org 23810912Sandreas.sandberg@arm.comdef switchCpus(system, cpuList, verbose=True): 2399521SAndreas.Sandberg@ARM.com """Switch CPUs in a system. 2404762Snate@binkert.org 2419521SAndreas.Sandberg@ARM.com Note: This method may switch the memory mode of the system if that 2429521SAndreas.Sandberg@ARM.com is required by the CPUs. It may also flush all caches in the 2439521SAndreas.Sandberg@ARM.com system. 2449521SAndreas.Sandberg@ARM.com 2459521SAndreas.Sandberg@ARM.com Arguments: 2469521SAndreas.Sandberg@ARM.com system -- Simulated system. 2479521SAndreas.Sandberg@ARM.com cpuList -- (old_cpu, new_cpu) tuples 2489521SAndreas.Sandberg@ARM.com """ 2499980Ssteve.reinhardt@amd.com 2509980Ssteve.reinhardt@amd.com if verbose: 2519980Ssteve.reinhardt@amd.com print "switching cpus" 2529980Ssteve.reinhardt@amd.com 2534762Snate@binkert.org if not isinstance(cpuList, list): 2544762Snate@binkert.org raise RuntimeError, "Must pass a list to this function" 2554946Snate@binkert.org for item in cpuList: 2564946Snate@binkert.org if not isinstance(item, tuple) or len(item) != 2: 2574762Snate@binkert.org raise RuntimeError, "List must have tuples of (oldCPU,newCPU)" 2584762Snate@binkert.org 2599521SAndreas.Sandberg@ARM.com old_cpus = [old_cpu for old_cpu, new_cpu in cpuList] 2609521SAndreas.Sandberg@ARM.com new_cpus = [new_cpu for old_cpu, new_cpu in cpuList] 2619521SAndreas.Sandberg@ARM.com old_cpu_set = set(old_cpus) 2629521SAndreas.Sandberg@ARM.com memory_mode_name = new_cpus[0].memory_mode() 2634946Snate@binkert.org for old_cpu, new_cpu in cpuList: 2644946Snate@binkert.org if not isinstance(old_cpu, objects.BaseCPU): 2654946Snate@binkert.org raise TypeError, "%s is not of type BaseCPU" % old_cpu 2664946Snate@binkert.org if not isinstance(new_cpu, objects.BaseCPU): 2674946Snate@binkert.org raise TypeError, "%s is not of type BaseCPU" % new_cpu 2689430SAndreas.Sandberg@ARM.com if new_cpu in old_cpu_set: 2699430SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2709430SAndreas.Sandberg@ARM.com "New CPU (%s) is in the list of old CPUs." % (old_cpu,) 2719430SAndreas.Sandberg@ARM.com if not new_cpu.switchedOut(): 2729430SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2739430SAndreas.Sandberg@ARM.com "New CPU (%s) is already active." % (new_cpu,) 2749521SAndreas.Sandberg@ARM.com if not new_cpu.support_take_over(): 2759521SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2769521SAndreas.Sandberg@ARM.com "New CPU (%s) does not support CPU handover." % (old_cpu,) 2779521SAndreas.Sandberg@ARM.com if new_cpu.memory_mode() != memory_mode_name: 2789521SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2799521SAndreas.Sandberg@ARM.com "%s and %s require different memory modes." % (new_cpu, 2809521SAndreas.Sandberg@ARM.com new_cpus[0]) 2819430SAndreas.Sandberg@ARM.com if old_cpu.switchedOut(): 2829430SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2839430SAndreas.Sandberg@ARM.com "Old CPU (%s) is inactive." % (new_cpu,) 2849521SAndreas.Sandberg@ARM.com if not old_cpu.support_take_over(): 2859521SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2869521SAndreas.Sandberg@ARM.com "Old CPU (%s) does not support CPU handover." % (old_cpu,) 2879521SAndreas.Sandberg@ARM.com 2889521SAndreas.Sandberg@ARM.com try: 2899521SAndreas.Sandberg@ARM.com memory_mode = _memory_modes[memory_mode_name] 2909521SAndreas.Sandberg@ARM.com except KeyError: 2919521SAndreas.Sandberg@ARM.com raise RuntimeError, "Invalid memory mode (%s)" % memory_mode_name 2929521SAndreas.Sandberg@ARM.com 29310912Sandreas.sandberg@arm.com drain() 2944762Snate@binkert.org 2954946Snate@binkert.org # Now all of the CPUs are ready to be switched out 2964946Snate@binkert.org for old_cpu, new_cpu in cpuList: 2979254SAndreas.Sandberg@arm.com old_cpu.switchOut() 2984762Snate@binkert.org 2999521SAndreas.Sandberg@ARM.com # Change the memory mode if required. We check if this is needed 3009521SAndreas.Sandberg@ARM.com # to avoid printing a warning if no switch was performed. 3019521SAndreas.Sandberg@ARM.com if system.getMemoryMode() != memory_mode: 3029524SAndreas.Sandberg@ARM.com # Flush the memory system if we are switching to a memory mode 3039524SAndreas.Sandberg@ARM.com # that disables caches. This typically happens when switching to a 3049524SAndreas.Sandberg@ARM.com # hardware virtualized CPU. 3059524SAndreas.Sandberg@ARM.com if memory_mode == objects.params.atomic_noncaching: 3069524SAndreas.Sandberg@ARM.com memWriteback(system) 3079524SAndreas.Sandberg@ARM.com memInvalidate(system) 3089524SAndreas.Sandberg@ARM.com 3099521SAndreas.Sandberg@ARM.com _changeMemoryMode(system, memory_mode) 3109521SAndreas.Sandberg@ARM.com 3114946Snate@binkert.org for old_cpu, new_cpu in cpuList: 3124946Snate@binkert.org new_cpu.takeOverFrom(old_cpu) 3135523Snate@binkert.org 31411360Sandreas@sandberg.pp.sedef notifyFork(root): 31511360Sandreas@sandberg.pp.se for obj in root.descendants(): 31611360Sandreas@sandberg.pp.se obj.notifyFork() 31711360Sandreas@sandberg.pp.se 31811362Sandreas@sandberg.pp.sefork_count = 0 31911362Sandreas@sandberg.pp.sedef fork(simout="%(parent)s.f%(fork_seq)i"): 32011362Sandreas@sandberg.pp.se """Fork the simulator. 32111362Sandreas@sandberg.pp.se 32211362Sandreas@sandberg.pp.se This function forks the simulator. After forking the simulator, 32311362Sandreas@sandberg.pp.se the child process gets its output files redirected to a new output 32411362Sandreas@sandberg.pp.se directory. The default name of the output directory is the same as 32511362Sandreas@sandberg.pp.se the parent with the suffix ".fN" added where N is the fork 32611362Sandreas@sandberg.pp.se sequence number. The name of the output directory can be 32711362Sandreas@sandberg.pp.se overridden using the simout keyword argument. 32811362Sandreas@sandberg.pp.se 32911362Sandreas@sandberg.pp.se Output file formatting dictionary: 33011362Sandreas@sandberg.pp.se parent -- Path to the parent process's output directory. 33111362Sandreas@sandberg.pp.se fork_seq -- Fork sequence number. 33211362Sandreas@sandberg.pp.se pid -- PID of the child process. 33311362Sandreas@sandberg.pp.se 33411362Sandreas@sandberg.pp.se Keyword Arguments: 33511362Sandreas@sandberg.pp.se simout -- New simulation output directory. 33611362Sandreas@sandberg.pp.se 33711362Sandreas@sandberg.pp.se Return Value: 33811362Sandreas@sandberg.pp.se pid of the child process or 0 if running in the child. 33911362Sandreas@sandberg.pp.se """ 34011362Sandreas@sandberg.pp.se from m5 import options 34111362Sandreas@sandberg.pp.se global fork_count 34211362Sandreas@sandberg.pp.se 34311802Sandreas.sandberg@arm.com if not _m5.core.listenersDisabled(): 34411362Sandreas@sandberg.pp.se raise RuntimeError, "Can not fork a simulator with listeners enabled" 34511362Sandreas@sandberg.pp.se 34611362Sandreas@sandberg.pp.se drain() 34711362Sandreas@sandberg.pp.se 34811362Sandreas@sandberg.pp.se try: 34911362Sandreas@sandberg.pp.se pid = os.fork() 35011362Sandreas@sandberg.pp.se except OSError, e: 35111362Sandreas@sandberg.pp.se raise e 35211362Sandreas@sandberg.pp.se 35311362Sandreas@sandberg.pp.se if pid == 0: 35411362Sandreas@sandberg.pp.se # In child, notify objects of the fork 35511362Sandreas@sandberg.pp.se root = objects.Root.getInstance() 35611362Sandreas@sandberg.pp.se notifyFork(root) 35711362Sandreas@sandberg.pp.se # Setup a new output directory 35811362Sandreas@sandberg.pp.se parent = options.outdir 35911362Sandreas@sandberg.pp.se options.outdir = simout % { 36011362Sandreas@sandberg.pp.se "parent" : parent, 36111362Sandreas@sandberg.pp.se "fork_seq" : fork_count, 36211362Sandreas@sandberg.pp.se "pid" : os.getpid(), 36311362Sandreas@sandberg.pp.se } 36411802Sandreas.sandberg@arm.com _m5.core.setOutputDir(options.outdir) 36511362Sandreas@sandberg.pp.se else: 36611362Sandreas@sandberg.pp.se fork_count += 1 36711362Sandreas@sandberg.pp.se 36811362Sandreas@sandberg.pp.se return pid 36911362Sandreas@sandberg.pp.se 37011802Sandreas.sandberg@arm.comfrom _m5.core import disableAllListeners, listenersDisabled 37112011Sgabeblack@google.comfrom _m5.core import listenersLoopbackOnly 37211802Sandreas.sandberg@arm.comfrom _m5.core import curTick 373