simulate.py revision 11360
18999Suri.wiener@arm.com# Copyright (c) 2012 ARM Limited 28999Suri.wiener@arm.com# All rights reserved. 38999Suri.wiener@arm.com# 48999Suri.wiener@arm.com# The license below extends only to copyright in the software and shall 58999Suri.wiener@arm.com# not be construed as granting a license to any other intellectual 68999Suri.wiener@arm.com# property including but not limited to intellectual property relating 78999Suri.wiener@arm.com# to a hardware implementation of the functionality of the software 88999Suri.wiener@arm.com# licensed hereunder. You may use the software subject to the license 98999Suri.wiener@arm.com# terms below provided that you ensure that this notice is replicated 108999Suri.wiener@arm.com# unmodified and in its entirety in all distributions of the software, 118999Suri.wiener@arm.com# modified or unmodified, in source code or in binary form. 128999Suri.wiener@arm.com# 134762Snate@binkert.org# Copyright (c) 2005 The Regents of The University of Michigan 147534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 154762Snate@binkert.org# All rights reserved. 164762Snate@binkert.org# 174762Snate@binkert.org# Redistribution and use in source and binary forms, with or without 184762Snate@binkert.org# modification, are permitted provided that the following conditions are 194762Snate@binkert.org# met: redistributions of source code must retain the above copyright 204762Snate@binkert.org# notice, this list of conditions and the following disclaimer; 214762Snate@binkert.org# redistributions in binary form must reproduce the above copyright 224762Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 234762Snate@binkert.org# documentation and/or other materials provided with the distribution; 244762Snate@binkert.org# neither the name of the copyright holders nor the names of its 254762Snate@binkert.org# contributors may be used to endorse or promote products derived from 264762Snate@binkert.org# this software without specific prior written permission. 274762Snate@binkert.org# 284762Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294762Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304762Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314762Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324762Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334762Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344762Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354762Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364762Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374762Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384762Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394762Snate@binkert.org# 404762Snate@binkert.org# Authors: Nathan Binkert 414762Snate@binkert.org# Steve Reinhardt 424762Snate@binkert.org 434762Snate@binkert.orgimport atexit 444762Snate@binkert.orgimport os 454762Snate@binkert.orgimport sys 464762Snate@binkert.org 474762Snate@binkert.org# import the SWIG-wrapped main C++ functions 484762Snate@binkert.orgimport internal 496001Snate@binkert.orgimport core 506001Snate@binkert.orgimport stats 514762Snate@binkert.orgimport SimObject 524762Snate@binkert.orgimport ticks 534851Snate@binkert.orgimport objects 548999Suri.wiener@arm.comfrom m5.util.dot_writer import do_dot 559262Ssascha.bischoff@arm.comfrom m5.internal.stats import updateEvents as updateStatEvents 568999Suri.wiener@arm.com 577525Ssteve.reinhardt@amd.comfrom util import fatal 588664SAli.Saidi@ARM.comfrom util import attrdict 594762Snate@binkert.org 609811Sandreas.hansson@arm.com# define a MaxTick parameter, unsigned 64 bit 619811Sandreas.hansson@arm.comMaxTick = 2**64 - 1 626654Snate@binkert.org 639521SAndreas.Sandberg@ARM.com_memory_modes = { 649521SAndreas.Sandberg@ARM.com "atomic" : objects.params.atomic, 659521SAndreas.Sandberg@ARM.com "timing" : objects.params.timing, 669524SAndreas.Sandberg@ARM.com "atomic_noncaching" : objects.params.atomic_noncaching, 679521SAndreas.Sandberg@ARM.com } 689521SAndreas.Sandberg@ARM.com 6910912Sandreas.sandberg@arm.com_drain_manager = internal.drain.DrainManager.instance() 7010912Sandreas.sandberg@arm.com 714762Snate@binkert.org# The final hook to generate .ini files. Called from the user script 724762Snate@binkert.org# once the config is built. 737531Ssteve.reinhardt@amd.comdef instantiate(ckpt_dir=None): 748245Snate@binkert.org from m5 import options 758234Snate@binkert.org 767525Ssteve.reinhardt@amd.com root = objects.Root.getInstance() 777525Ssteve.reinhardt@amd.com 787525Ssteve.reinhardt@amd.com if not root: 797525Ssteve.reinhardt@amd.com fatal("Need to instantiate Root() before calling instantiate()") 807525Ssteve.reinhardt@amd.com 814762Snate@binkert.org # we need to fix the global frequency 824762Snate@binkert.org ticks.fixGlobalFrequency() 834762Snate@binkert.org 847528Ssteve.reinhardt@amd.com # Make sure SimObject-valued params are in the configuration 857528Ssteve.reinhardt@amd.com # hierarchy so we catch them with future descendants() walks 867528Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.adoptOrphanParams() 877528Ssteve.reinhardt@amd.com 887527Ssteve.reinhardt@amd.com # Unproxy in sorted order for determinism 897527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.unproxyParams() 905037Smilesck@eecs.umich.edu 915773Snate@binkert.org if options.dump_config: 925773Snate@binkert.org ini_file = file(os.path.join(options.outdir, options.dump_config), 'w') 937527Ssteve.reinhardt@amd.com # Print ini sections in sorted order for easier diffing 947527Ssteve.reinhardt@amd.com for obj in sorted(root.descendants(), key=lambda o: o.path()): 957527Ssteve.reinhardt@amd.com obj.print_ini(ini_file) 965773Snate@binkert.org ini_file.close() 974762Snate@binkert.org 988664SAli.Saidi@ARM.com if options.json_config: 998675SAli.Saidi@ARM.com try: 1008675SAli.Saidi@ARM.com import json 1018675SAli.Saidi@ARM.com json_file = file(os.path.join(options.outdir, options.json_config), 'w') 1028675SAli.Saidi@ARM.com d = root.get_config_as_dict() 1038675SAli.Saidi@ARM.com json.dump(d, json_file, indent=4) 1048675SAli.Saidi@ARM.com json_file.close() 1058675SAli.Saidi@ARM.com except ImportError: 1068675SAli.Saidi@ARM.com pass 1078664SAli.Saidi@ARM.com 1088999Suri.wiener@arm.com do_dot(root, options.outdir, options.dot_config) 1098664SAli.Saidi@ARM.com 1104762Snate@binkert.org # Initialize the global statistics 1116001Snate@binkert.org stats.initSimStats() 1124762Snate@binkert.org 1134762Snate@binkert.org # Create the C++ sim objects and connect ports 1147527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.createCCObject() 1157527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.connectPorts() 1164762Snate@binkert.org 1174762Snate@binkert.org # Do a second pass to finish initializing the sim objects 1187527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.init() 1194762Snate@binkert.org 1204762Snate@binkert.org # Do a third pass to initialize statistics 1217527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.regStats() 1224762Snate@binkert.org 12310023Smatt.horsnell@ARM.com # Do a fourth pass to initialize probe points 12410023Smatt.horsnell@ARM.com for obj in root.descendants(): obj.regProbePoints() 12510023Smatt.horsnell@ARM.com 12610023Smatt.horsnell@ARM.com # Do a fifth pass to connect probe listeners 12710023Smatt.horsnell@ARM.com for obj in root.descendants(): obj.regProbeListeners() 12810023Smatt.horsnell@ARM.com 1296001Snate@binkert.org # We're done registering statistics. Enable the stats package now. 1306001Snate@binkert.org stats.enable() 1314762Snate@binkert.org 1327531Ssteve.reinhardt@amd.com # Restore checkpoint (if any) 1337531Ssteve.reinhardt@amd.com if ckpt_dir: 13410912Sandreas.sandberg@arm.com _drain_manager.preCheckpointRestore() 1357532Ssteve.reinhardt@amd.com ckpt = internal.core.getCheckpoint(ckpt_dir) 1367532Ssteve.reinhardt@amd.com internal.core.unserializeGlobals(ckpt); 1377532Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.loadState(ckpt) 1387532Ssteve.reinhardt@amd.com else: 1397532Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.initState() 1407531Ssteve.reinhardt@amd.com 1419262Ssascha.bischoff@arm.com # Check to see if any of the stat events are in the past after resuming from 1429262Ssascha.bischoff@arm.com # a checkpoint, If so, this call will shift them to be at a valid time. 1439262Ssascha.bischoff@arm.com updateStatEvents() 1449262Ssascha.bischoff@arm.com 1454762Snate@binkert.orgneed_startup = True 1464762Snate@binkert.orgdef simulate(*args, **kwargs): 14710912Sandreas.sandberg@arm.com global need_startup 1484762Snate@binkert.org 1494762Snate@binkert.org if need_startup: 1507527Ssteve.reinhardt@amd.com root = objects.Root.getInstance() 1517527Ssteve.reinhardt@amd.com for obj in root.descendants(): obj.startup() 1524762Snate@binkert.org need_startup = False 1534762Snate@binkert.org 1549983Sstever@gmail.com # Python exit handlers happen in reverse order. 1559983Sstever@gmail.com # We want to dump stats last. 1569983Sstever@gmail.com atexit.register(stats.dump) 1579983Sstever@gmail.com 1589983Sstever@gmail.com # register our C++ exit callback function with Python 1599983Sstever@gmail.com atexit.register(internal.core.doExitCleanup) 1609983Sstever@gmail.com 1619993Snilay@cs.wisc.edu # Reset to put the stats in a consistent state. 1629993Snilay@cs.wisc.edu stats.reset() 1639993Snilay@cs.wisc.edu 16410912Sandreas.sandberg@arm.com if _drain_manager.isDrained(): 16510912Sandreas.sandberg@arm.com _drain_manager.resume() 1664762Snate@binkert.org 1674762Snate@binkert.org return internal.event.simulate(*args, **kwargs) 1684762Snate@binkert.org 1694762Snate@binkert.org# Export curTick to user script. 1704762Snate@binkert.orgdef curTick(): 1717823Ssteve.reinhardt@amd.com return internal.core.curTick() 1724762Snate@binkert.org 17310912Sandreas.sandberg@arm.comdef drain(): 17410912Sandreas.sandberg@arm.com """Drain the simulator in preparation of a checkpoint or memory mode 17510912Sandreas.sandberg@arm.com switch. 17610912Sandreas.sandberg@arm.com 17710912Sandreas.sandberg@arm.com This operation is a no-op if the simulator is already in the 17810912Sandreas.sandberg@arm.com Drained state. 17910912Sandreas.sandberg@arm.com 18010912Sandreas.sandberg@arm.com """ 18110912Sandreas.sandberg@arm.com 1829344SAndreas.Sandberg@arm.com # Try to drain all objects. Draining might not be completed unless 1839344SAndreas.Sandberg@arm.com # all objects return that they are drained on the first call. This 1849344SAndreas.Sandberg@arm.com # is because as objects drain they may cause other objects to no 1859344SAndreas.Sandberg@arm.com # longer be drained. 1869344SAndreas.Sandberg@arm.com def _drain(): 18710912Sandreas.sandberg@arm.com # Try to drain the system. The drain is successful if all 18810912Sandreas.sandberg@arm.com # objects are done without simulation. We need to simulate 18910912Sandreas.sandberg@arm.com # more if not. 19010912Sandreas.sandberg@arm.com if _drain_manager.tryDrain(): 19110912Sandreas.sandberg@arm.com return True 19210912Sandreas.sandberg@arm.com 19310912Sandreas.sandberg@arm.com # WARNING: if a valid exit event occurs while draining, it 19410912Sandreas.sandberg@arm.com # will not get returned to the user script 19510912Sandreas.sandberg@arm.com exit_event = internal.event.simulate() 19610912Sandreas.sandberg@arm.com while exit_event.getCause() != 'Finished drain': 19710436Slukefahr@umich.edu exit_event = simulate() 1989344SAndreas.Sandberg@arm.com 19910912Sandreas.sandberg@arm.com return False 20010912Sandreas.sandberg@arm.com 20110912Sandreas.sandberg@arm.com # Don't try to drain a system that is already drained 20210912Sandreas.sandberg@arm.com is_drained = _drain_manager.isDrained() 20310912Sandreas.sandberg@arm.com while not is_drained: 20410912Sandreas.sandberg@arm.com is_drained = _drain() 20510912Sandreas.sandberg@arm.com 20610912Sandreas.sandberg@arm.com assert _drain_manager.isDrained(), "Drain state inconsistent" 2074762Snate@binkert.org 2089346SAndreas.Sandberg@arm.comdef memWriteback(root): 2099346SAndreas.Sandberg@arm.com for obj in root.descendants(): 2109346SAndreas.Sandberg@arm.com obj.memWriteback() 2119346SAndreas.Sandberg@arm.com 2129346SAndreas.Sandberg@arm.comdef memInvalidate(root): 2139346SAndreas.Sandberg@arm.com for obj in root.descendants(): 2149346SAndreas.Sandberg@arm.com obj.memInvalidate() 2159346SAndreas.Sandberg@arm.com 2167525Ssteve.reinhardt@amd.comdef checkpoint(dir): 2177525Ssteve.reinhardt@amd.com root = objects.Root.getInstance() 2184762Snate@binkert.org if not isinstance(root, objects.Root): 2194762Snate@binkert.org raise TypeError, "Checkpoint must be called on a root object." 22010912Sandreas.sandberg@arm.com 22110912Sandreas.sandberg@arm.com drain() 2229346SAndreas.Sandberg@arm.com memWriteback(root) 2234762Snate@binkert.org print "Writing checkpoint" 2244859Snate@binkert.org internal.core.serializeAll(dir) 2254762Snate@binkert.org 2269521SAndreas.Sandberg@ARM.comdef _changeMemoryMode(system, mode): 2274762Snate@binkert.org if not isinstance(system, (objects.Root, objects.System)): 2284762Snate@binkert.org raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ 2294762Snate@binkert.org (type(system), objects.Root, objects.System) 2309343SAndreas.Sandberg@arm.com if system.getMemoryMode() != mode: 2319343SAndreas.Sandberg@arm.com system.setMemoryMode(mode) 2329343SAndreas.Sandberg@arm.com else: 2339343SAndreas.Sandberg@arm.com print "System already in target mode. Memory mode unchanged." 2344762Snate@binkert.org 23510912Sandreas.sandberg@arm.comdef switchCpus(system, cpuList, verbose=True): 2369521SAndreas.Sandberg@ARM.com """Switch CPUs in a system. 2374762Snate@binkert.org 2389521SAndreas.Sandberg@ARM.com Note: This method may switch the memory mode of the system if that 2399521SAndreas.Sandberg@ARM.com is required by the CPUs. It may also flush all caches in the 2409521SAndreas.Sandberg@ARM.com system. 2419521SAndreas.Sandberg@ARM.com 2429521SAndreas.Sandberg@ARM.com Arguments: 2439521SAndreas.Sandberg@ARM.com system -- Simulated system. 2449521SAndreas.Sandberg@ARM.com cpuList -- (old_cpu, new_cpu) tuples 2459521SAndreas.Sandberg@ARM.com """ 2469980Ssteve.reinhardt@amd.com 2479980Ssteve.reinhardt@amd.com if verbose: 2489980Ssteve.reinhardt@amd.com print "switching cpus" 2499980Ssteve.reinhardt@amd.com 2504762Snate@binkert.org if not isinstance(cpuList, list): 2514762Snate@binkert.org raise RuntimeError, "Must pass a list to this function" 2524946Snate@binkert.org for item in cpuList: 2534946Snate@binkert.org if not isinstance(item, tuple) or len(item) != 2: 2544762Snate@binkert.org raise RuntimeError, "List must have tuples of (oldCPU,newCPU)" 2554762Snate@binkert.org 2569521SAndreas.Sandberg@ARM.com old_cpus = [old_cpu for old_cpu, new_cpu in cpuList] 2579521SAndreas.Sandberg@ARM.com new_cpus = [new_cpu for old_cpu, new_cpu in cpuList] 2589521SAndreas.Sandberg@ARM.com old_cpu_set = set(old_cpus) 2599521SAndreas.Sandberg@ARM.com memory_mode_name = new_cpus[0].memory_mode() 2604946Snate@binkert.org for old_cpu, new_cpu in cpuList: 2614946Snate@binkert.org if not isinstance(old_cpu, objects.BaseCPU): 2624946Snate@binkert.org raise TypeError, "%s is not of type BaseCPU" % old_cpu 2634946Snate@binkert.org if not isinstance(new_cpu, objects.BaseCPU): 2644946Snate@binkert.org raise TypeError, "%s is not of type BaseCPU" % new_cpu 2659430SAndreas.Sandberg@ARM.com if new_cpu in old_cpu_set: 2669430SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2679430SAndreas.Sandberg@ARM.com "New CPU (%s) is in the list of old CPUs." % (old_cpu,) 2689430SAndreas.Sandberg@ARM.com if not new_cpu.switchedOut(): 2699430SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2709430SAndreas.Sandberg@ARM.com "New CPU (%s) is already active." % (new_cpu,) 2719521SAndreas.Sandberg@ARM.com if not new_cpu.support_take_over(): 2729521SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2739521SAndreas.Sandberg@ARM.com "New CPU (%s) does not support CPU handover." % (old_cpu,) 2749521SAndreas.Sandberg@ARM.com if new_cpu.memory_mode() != memory_mode_name: 2759521SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2769521SAndreas.Sandberg@ARM.com "%s and %s require different memory modes." % (new_cpu, 2779521SAndreas.Sandberg@ARM.com new_cpus[0]) 2789430SAndreas.Sandberg@ARM.com if old_cpu.switchedOut(): 2799430SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2809430SAndreas.Sandberg@ARM.com "Old CPU (%s) is inactive." % (new_cpu,) 2819521SAndreas.Sandberg@ARM.com if not old_cpu.support_take_over(): 2829521SAndreas.Sandberg@ARM.com raise RuntimeError, \ 2839521SAndreas.Sandberg@ARM.com "Old CPU (%s) does not support CPU handover." % (old_cpu,) 2849521SAndreas.Sandberg@ARM.com 2859521SAndreas.Sandberg@ARM.com try: 2869521SAndreas.Sandberg@ARM.com memory_mode = _memory_modes[memory_mode_name] 2879521SAndreas.Sandberg@ARM.com except KeyError: 2889521SAndreas.Sandberg@ARM.com raise RuntimeError, "Invalid memory mode (%s)" % memory_mode_name 2899521SAndreas.Sandberg@ARM.com 29010912Sandreas.sandberg@arm.com drain() 2914762Snate@binkert.org 2924946Snate@binkert.org # Now all of the CPUs are ready to be switched out 2934946Snate@binkert.org for old_cpu, new_cpu in cpuList: 2949254SAndreas.Sandberg@arm.com old_cpu.switchOut() 2954762Snate@binkert.org 2969521SAndreas.Sandberg@ARM.com # Change the memory mode if required. We check if this is needed 2979521SAndreas.Sandberg@ARM.com # to avoid printing a warning if no switch was performed. 2989521SAndreas.Sandberg@ARM.com if system.getMemoryMode() != memory_mode: 2999524SAndreas.Sandberg@ARM.com # Flush the memory system if we are switching to a memory mode 3009524SAndreas.Sandberg@ARM.com # that disables caches. This typically happens when switching to a 3019524SAndreas.Sandberg@ARM.com # hardware virtualized CPU. 3029524SAndreas.Sandberg@ARM.com if memory_mode == objects.params.atomic_noncaching: 3039524SAndreas.Sandberg@ARM.com memWriteback(system) 3049524SAndreas.Sandberg@ARM.com memInvalidate(system) 3059524SAndreas.Sandberg@ARM.com 3069521SAndreas.Sandberg@ARM.com _changeMemoryMode(system, memory_mode) 3079521SAndreas.Sandberg@ARM.com 3084946Snate@binkert.org for old_cpu, new_cpu in cpuList: 3094946Snate@binkert.org new_cpu.takeOverFrom(old_cpu) 3105523Snate@binkert.org 31111360Sandreas@sandberg.pp.sedef notifyFork(root): 31211360Sandreas@sandberg.pp.se for obj in root.descendants(): 31311360Sandreas@sandberg.pp.se obj.notifyFork() 31411360Sandreas@sandberg.pp.se 3155523Snate@binkert.orgfrom internal.core import disableAllListeners 316