inst.proto revision 12602:69eb7c6e5f7f
16019Shines@cs.fsu.edu// Copyright (c) 2014,2017 ARM Limited
211577SDylan.Johnson@ARM.com// All rights reserved
37399SAli.Saidi@ARM.com//
47399SAli.Saidi@ARM.com// The license below extends only to copyright in the software and shall
57399SAli.Saidi@ARM.com// not be construed as granting a license to any other intellectual
67399SAli.Saidi@ARM.com// property including but not limited to intellectual property relating
77399SAli.Saidi@ARM.com// to a hardware implementation of the functionality of the software
87399SAli.Saidi@ARM.com// licensed hereunder.  You may use the software subject to the license
97399SAli.Saidi@ARM.com// terms below provided that you ensure that this notice is replicated
107399SAli.Saidi@ARM.com// unmodified and in its entirety in all distributions of the software,
117399SAli.Saidi@ARM.com// modified or unmodified, in source code or in binary form.
127399SAli.Saidi@ARM.com//
137399SAli.Saidi@ARM.com// Redistribution and use in source and binary forms, with or without
146019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are
156019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright
166019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer;
176019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright
186019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the
196019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution;
206019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its
216019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from
226019Shines@cs.fsu.edu// this software without specific prior written permission.
236019Shines@cs.fsu.edu//
246019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
256019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
266019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
276019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
286019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
296019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
306019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
316019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
326019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
336019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
346019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
356019Shines@cs.fsu.edu//
366019Shines@cs.fsu.edu// Authors: Ali Saidi
376019Shines@cs.fsu.edu
386019Shines@cs.fsu.edusyntax = "proto2";
396019Shines@cs.fsu.edu
407399SAli.Saidi@ARM.com// Put all the generated messages in a namespace
416019Shines@cs.fsu.edupackage ProtoMessage;
426019Shines@cs.fsu.edu
436019Shines@cs.fsu.edu// Packet header with the identifier describing what object captured
446019Shines@cs.fsu.edu// the trace, the version of this file format, and the tick frequency
456019Shines@cs.fsu.edu// for all the packet time stamps.
466019Shines@cs.fsu.edumessage InstHeader {
476019Shines@cs.fsu.edu  required string obj_id = 1;
488229Snate@binkert.org  required uint32 ver = 2 [default = 0];
496019Shines@cs.fsu.edu  required uint64 tick_freq = 3;
506019Shines@cs.fsu.edu  required bool has_mem = 4;
5110687SAndreas.Sandberg@ARM.com}
526019Shines@cs.fsu.edu
536019Shines@cs.fsu.edumessage Inst {
546116Snate@binkert.org  required uint64 pc = 1;
5510463SAndreas.Sandberg@ARM.com  oneof inst_oneof {
566019Shines@cs.fsu.edu    fixed32 inst = 2;
576019Shines@cs.fsu.edu    bytes inst_bytes = 9;
586019Shines@cs.fsu.edu  }
596019Shines@cs.fsu.edu  optional uint32 nodeid = 3;
606019Shines@cs.fsu.edu  optional uint32 cpuid = 4;
617404SAli.Saidi@ARM.com  optional fixed64 tick = 5;
6210037SARM gem5 Developers
6310037SARM gem5 Developers  enum InstType {
6411395Sandreas.sandberg@arm.com    None = 0;
6511395Sandreas.sandberg@arm.com    IntAlu = 1;
6611395Sandreas.sandberg@arm.com    IntMul = 2;
6711395Sandreas.sandberg@arm.com    IntDiv = 3;
6811395Sandreas.sandberg@arm.com    FloatAdd = 4;
6911395Sandreas.sandberg@arm.com    FloatCmp = 5;
7011395Sandreas.sandberg@arm.com    FloatCvt = 6;
7111395Sandreas.sandberg@arm.com    FloatMult = 7;
7211395Sandreas.sandberg@arm.com    FloatDiv = 8;
7311395Sandreas.sandberg@arm.com    FloatSqrt = 9;
7411395Sandreas.sandberg@arm.com    SIMDIntAdd = 10;
7511395Sandreas.sandberg@arm.com    SIMDIntAddAcc = 11;
7611395Sandreas.sandberg@arm.com    SIMDIntAlu = 12;
7711395Sandreas.sandberg@arm.com    SIMDIntCmp = 13;
7811395Sandreas.sandberg@arm.com    SIMDIntCvt = 14;
7911395Sandreas.sandberg@arm.com    SIMDMisc = 15;
8011395Sandreas.sandberg@arm.com    SIMDIntMult = 16;
8111395Sandreas.sandberg@arm.com    SIMDIntMultAcc = 17;
8211395Sandreas.sandberg@arm.com    SIMDIntShift = 18;
8311395Sandreas.sandberg@arm.com    SIMDIntShiftAcc = 19;
8411395Sandreas.sandberg@arm.com    SIMDSqrt = 20;
8511395Sandreas.sandberg@arm.com    SIMDFloatAdd = 21;
8611395Sandreas.sandberg@arm.com    SIMDFloatAlu = 22;
8711395Sandreas.sandberg@arm.com    SIMDFloatCmp = 23;
8811395Sandreas.sandberg@arm.com    SIMDFloatCvt = 24;
8911395Sandreas.sandberg@arm.com    SIMDFloatDiv = 25;
9011395Sandreas.sandberg@arm.com    SIMDFloatMisc = 26;
9111395Sandreas.sandberg@arm.com    SIMDFloatMult = 27;
9211395Sandreas.sandberg@arm.com    SIMDFloatMultAdd = 28;
9311395Sandreas.sandberg@arm.com    SIMDFloatSqrt = 29;
9411395Sandreas.sandberg@arm.com    MemRead = 30;
9511395Sandreas.sandberg@arm.com    MemWrite = 31;
9611395Sandreas.sandberg@arm.com    IprAccess = 32;
9711395Sandreas.sandberg@arm.com    InstPrefetch = 33;
9811395Sandreas.sandberg@arm.com  }
9911395Sandreas.sandberg@arm.com
10011395Sandreas.sandberg@arm.com  optional InstType type = 6; // add, mul, fp add, load, store, simd add, …
1017404SAli.Saidi@ARM.com  optional uint32 inst_flags = 7; // execution mode information
1026019Shines@cs.fsu.edu
1036019Shines@cs.fsu.edu  // If the operation does one or more memory accesses
1047294Sgblack@eecs.umich.edu  message MemAccess {
1057294Sgblack@eecs.umich.edu      required uint64 addr = 1;
10610037SARM gem5 Developers      required uint32 size = 2;
1077294Sgblack@eecs.umich.edu      optional uint32 mem_flags = 3;
1087294Sgblack@eecs.umich.edu  }
1097294Sgblack@eecs.umich.edu  repeated MemAccess mem_access = 8;
11010037SARM gem5 Developers}
11110037SARM gem5 Developers
11210037SARM gem5 Developers