xbar.hh revision 9291
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Ali Saidi 42 * Andreas Hansson 43 * William Wang 44 */ 45 46/** 47 * @file 48 * Declaration of an abstract bus base class. 49 */ 50 51#ifndef __MEM_BUS_HH__ 52#define __MEM_BUS_HH__ 53 54#include <deque> 55#include <set> 56 57#include "base/addr_range_map.hh" 58#include "base/types.hh" 59#include "mem/mem_object.hh" 60#include "params/BaseBus.hh" 61 62/** 63 * The base bus contains the common elements of the non-coherent and 64 * coherent bus. It is an abstract class that does not have any of the 65 * functionality relating to the actual reception and transmission of 66 * packets, as this is left for the subclasses. 67 * 68 * The BaseBus is responsible for the basic flow control (busy or 69 * not), the administration of retries, and the address decoding. 70 */ 71class BaseBus : public MemObject 72{ 73 74 protected: 75 76 /** 77 * A bus layer is an internal bus structure with its own flow 78 * control and arbitration. Hence, a single-layer bus mimics a 79 * traditional off-chip tri-state bus (like PCI), where only one 80 * set of wires are shared. For on-chip buses, a good starting 81 * point is to have three layers, for requests, responses, and 82 * snoop responses respectively (snoop requests are instantaneous 83 * and do not need any flow control or arbitration). This case is 84 * similar to AHB and some OCP configurations. 85 * 86 * As a further extensions beyond the three-layer bus, a future 87 * multi-layer bus has with one layer per connected slave port 88 * provides a full or partial crossbar, like AXI, OCP, PCIe etc. 89 * 90 * The template parameter, PortClass, indicates the destination 91 * port type for the bus. The retry list holds either master ports 92 * or slave ports, depending on the direction of the layer. Thus, 93 * a request layer has a retry list containing slave ports, 94 * whereas a response layer holds master ports. 95 */ 96 template <typename PortClass> 97 class Layer 98 { 99 100 public: 101 102 /** 103 * Create a bus layer and give it a name. The bus layer uses 104 * the bus an event manager. 105 * 106 * @param _bus the bus this layer belongs to 107 * @param _name the layer's name 108 * @param _clock clock period in ticks 109 */ 110 Layer(BaseBus& _bus, const std::string& _name, Tick _clock); 111 112 /** 113 * Drain according to the normal semantics, so that the bus 114 * can tell the layer to drain, and pass an event to signal 115 * back when drained. 116 * 117 * @param de drain event to call once drained 118 * 119 * @return 1 if busy or waiting to retry, or 0 if idle 120 */ 121 unsigned int drain(Event *de); 122 123 /** 124 * Get the bus layer's name 125 */ 126 const std::string name() const { return bus.name() + _name; } 127 128 129 /** 130 * Determine if the bus layer accepts a packet from a specific 131 * port. If not, the port in question is also added to the 132 * retry list. In either case the state of the layer is updated 133 * accordingly. 134 * 135 * @param port Source port resenting the packet 136 * 137 * @return True if the bus layer accepts the packet 138 */ 139 bool tryTiming(PortClass* port); 140 141 /** 142 * Deal with a destination port accepting a packet by potentially 143 * removing the source port from the retry list (if retrying) and 144 * occupying the bus layer accordingly. 145 * 146 * @param busy_time Time to spend as a result of a successful send 147 */ 148 void succeededTiming(Tick busy_time); 149 150 /** 151 * Deal with a destination port not accepting a packet by 152 * potentially adding the source port to the retry list (if 153 * not already at the front) and occupying the bus layer 154 * accordingly. 155 * 156 * @param busy_time Time to spend as a result of a failed send 157 */ 158 void failedTiming(PortClass* port, Tick busy_time); 159 160 /** Occupy the bus layer until until */ 161 void occupyLayer(Tick until); 162 163 /** 164 * Send a retry to the port at the head of the retryList. The 165 * caller must ensure that the list is not empty. 166 */ 167 void retryWaiting(); 168 169 /** 170 * Handler a retry from a neighbouring module. Eventually this 171 * should be all encapsulated in the bus. This wraps 172 * retryWaiting by verifying that there are ports waiting 173 * before calling retryWaiting. 174 */ 175 void recvRetry(); 176 177 private: 178 179 /** The bus this layer is a part of. */ 180 BaseBus& bus; 181 182 /** A name for this layer. */ 183 std::string _name; 184 185 /** 186 * We declare an enum to track the state of the bus layer. The 187 * starting point is an idle state where the bus layer is 188 * waiting for a packet to arrive. Upon arrival, the bus layer 189 * transitions to the busy state, where it remains either 190 * until the packet transfer is done, or the header time is 191 * spent. Once the bus layer leaves the busy state, it can 192 * either go back to idle, if no packets have arrived while it 193 * was busy, or the bus layer goes on to retry the first port 194 * on the retryList. A similar transition takes place from 195 * idle to retry if the bus layer receives a retry from one of 196 * its connected ports. The retry state lasts until the port 197 * in questions calls sendTiming and returns control to the 198 * bus layer, or goes to a busy state if the port does not 199 * immediately react to the retry by calling sendTiming. 200 */ 201 enum State { IDLE, BUSY, RETRY }; 202 203 /** track the state of the bus layer */ 204 State state; 205 206 /** the clock speed for the bus layer */ 207 Tick clock; 208 209 /** event for signalling when drained */ 210 Event * drainEvent; 211 212 /** 213 * An array of ports that retry should be called 214 * on because the original send failed for whatever reason. 215 */ 216 std::deque<PortClass*> retryList; 217 218 /** 219 * Release the bus layer after being occupied and return to an 220 * idle state where we proceed to send a retry to any 221 * potential waiting port, or drain if asked to do so. 222 */ 223 void releaseLayer(); 224 225 /** event used to schedule a release of the layer */ 226 EventWrapper<Layer, &Layer::releaseLayer> releaseEvent; 227 228 }; 229 230 /** cycles of overhead per transaction */ 231 const Cycles headerCycles; 232 /** the width of the bus in bytes */ 233 const uint32_t width; 234 235 typedef AddrRangeMap<PortID>::iterator PortMapIter; 236 typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter; 237 AddrRangeMap<PortID> portMap; 238 239 AddrRange defaultRange; 240 241 /** 242 * Function called by the port when the bus is recieving a range change. 243 * 244 * @param master_port_id id of the port that received the change 245 */ 246 void recvRangeChange(PortID master_port_id); 247 248 /** Find which port connected to this bus (if any) should be given a packet 249 * with this address. 250 * @param addr Address to find port for. 251 * @return id of port that the packet should be sent out of. 252 */ 253 PortID findPort(Addr addr); 254 255 // Cache for the findPort function storing recently used ports from portMap 256 struct PortCache { 257 bool valid; 258 PortID id; 259 AddrRange range; 260 }; 261 262 PortCache portCache[3]; 263 264 // Checks the cache and returns the id of the port that has the requested 265 // address within its range 266 inline PortID checkPortCache(Addr addr) const { 267 if (portCache[0].valid && portCache[0].range == addr) { 268 return portCache[0].id; 269 } 270 if (portCache[1].valid && portCache[1].range == addr) { 271 return portCache[1].id; 272 } 273 if (portCache[2].valid && portCache[2].range == addr) { 274 return portCache[2].id; 275 } 276 277 return InvalidPortID; 278 } 279 280 // Clears the earliest entry of the cache and inserts a new port entry 281 inline void updatePortCache(short id, const AddrRange& range) { 282 portCache[2].valid = portCache[1].valid; 283 portCache[2].id = portCache[1].id; 284 portCache[2].range = portCache[1].range; 285 286 portCache[1].valid = portCache[0].valid; 287 portCache[1].id = portCache[0].id; 288 portCache[1].range = portCache[0].range; 289 290 portCache[0].valid = true; 291 portCache[0].id = id; 292 portCache[0].range = range; 293 } 294 295 // Clears the cache. Needs to be called in constructor. 296 inline void clearPortCache() { 297 portCache[2].valid = false; 298 portCache[1].valid = false; 299 portCache[0].valid = false; 300 } 301 302 /** 303 * Return the address ranges the bus is responsible for. 304 * 305 * @return a list of non-overlapping address ranges 306 */ 307 AddrRangeList getAddrRanges() const; 308 309 /** Calculate the timing parameters for the packet. Updates the 310 * firstWordTime and finishTime fields of the packet object. 311 * Returns the tick at which the packet header is completed (which 312 * will be all that is sent if the target rejects the packet). 313 */ 314 Tick calcPacketTiming(PacketPtr pkt); 315 316 /** 317 * Ask everyone on the bus what their size is and determine the 318 * bus size as either the maximum, or if no device specifies a 319 * block size return the default. 320 * 321 * @return the max of all the sizes or the default if none is set 322 */ 323 unsigned deviceBlockSize() const; 324 325 /** 326 * Remember for each of the master ports of the bus if we got an 327 * address range from the connected slave. For convenience, also 328 * keep track of if we got ranges from all the slave modules or 329 * not. 330 */ 331 std::vector<bool> gotAddrRanges; 332 bool gotAllAddrRanges; 333 334 /** The master and slave ports of the bus */ 335 std::vector<SlavePort*> slavePorts; 336 std::vector<MasterPort*> masterPorts; 337 338 /** Convenience typedefs. */ 339 typedef std::vector<SlavePort*>::iterator SlavePortIter; 340 typedef std::vector<MasterPort*>::iterator MasterPortIter; 341 typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter; 342 typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter; 343 344 /** Port that handles requests that don't match any of the interfaces.*/ 345 PortID defaultPortID; 346 347 /** If true, use address range provided by default device. Any 348 address not handled by another port and not in default device's 349 range will cause a fatal error. If false, just send all 350 addresses not handled by another port to default device. */ 351 const bool useDefaultRange; 352 353 uint32_t blockSize; 354 355 BaseBus(const BaseBusParams *p); 356 357 virtual ~BaseBus(); 358 359 public: 360 361 virtual void init(); 362 363 /** A function used to return the port associated with this bus object. */ 364 virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1); 365 virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1); 366 367 virtual unsigned int drain(Event *de) = 0; 368 369}; 370 371#endif //__MEM_BUS_HH__ 372