xbar.hh revision 9342
12207SN/A/* 22207SN/A * Copyright (c) 2011-2012 ARM Limited 32207SN/A * All rights reserved 42207SN/A * 52207SN/A * The license below extends only to copyright in the software and shall 62207SN/A * not be construed as granting a license to any other intellectual 72207SN/A * property including but not limited to intellectual property relating 82207SN/A * to a hardware implementation of the functionality of the software 92207SN/A * licensed hereunder. You may use the software subject to the license 102207SN/A * terms below provided that you ensure that this notice is replicated 112207SN/A * unmodified and in its entirety in all distributions of the software, 122207SN/A * modified or unmodified, in source code or in binary form. 132207SN/A * 142207SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152207SN/A * All rights reserved. 162207SN/A * 172207SN/A * Redistribution and use in source and binary forms, with or without 182207SN/A * modification, are permitted provided that the following conditions are 192207SN/A * met: redistributions of source code must retain the above copyright 202207SN/A * notice, this list of conditions and the following disclaimer; 212207SN/A * redistributions in binary form must reproduce the above copyright 222207SN/A * notice, this list of conditions and the following disclaimer in the 232207SN/A * documentation and/or other materials provided with the distribution; 242207SN/A * neither the name of the copyright holders nor the names of its 252207SN/A * contributors may be used to endorse or promote products derived from 262207SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322972Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 348229Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352454SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362454SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372680Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 388232Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395759Shsul@eecs.umich.edu * 407678Sgblack@eecs.umich.edu * Authors: Ron Dreslinski 415759Shsul@eecs.umich.edu * Ali Saidi 422474SN/A * Andreas Hansson 432207SN/A * William Wang 442474SN/A */ 452474SN/A 462474SN/A/** 475569Snate@binkert.org * @file 485569Snate@binkert.org * Declaration of an abstract bus base class. 495154Sgblack@eecs.umich.edu */ 502474SN/A 512474SN/A#ifndef __MEM_BUS_HH__ 5210318Sandreas.hansson@arm.com#define __MEM_BUS_HH__ 532474SN/A 542474SN/A#include <deque> 552474SN/A#include <set> 562474SN/A 572474SN/A#include "base/addr_range_map.hh" 582474SN/A#include "base/types.hh" 592474SN/A#include "mem/mem_object.hh" 602474SN/A#include "params/BaseBus.hh" 612474SN/A 622474SN/A/** 632474SN/A * The base bus contains the common elements of the non-coherent and 642474SN/A * coherent bus. It is an abstract class that does not have any of the 652474SN/A * functionality relating to the actual reception and transmission of 662474SN/A * packets, as this is left for the subclasses. 672474SN/A * 685759Shsul@eecs.umich.edu * The BaseBus is responsible for the basic flow control (busy or 695759Shsul@eecs.umich.edu * not), the administration of retries, and the address decoding. 705759Shsul@eecs.umich.edu */ 715759Shsul@eecs.umich.educlass BaseBus : public MemObject 725771Shsul@eecs.umich.edu{ 735759Shsul@eecs.umich.edu 745759Shsul@eecs.umich.edu protected: 755759Shsul@eecs.umich.edu 765759Shsul@eecs.umich.edu /** 775759Shsul@eecs.umich.edu * A bus layer is an internal bus structure with its own flow 7811320Ssteve.reinhardt@amd.com * control and arbitration. Hence, a single-layer bus mimics a 795759Shsul@eecs.umich.edu * traditional off-chip tri-state bus (like PCI), where only one 805759Shsul@eecs.umich.edu * set of wires are shared. For on-chip buses, a good starting 815759Shsul@eecs.umich.edu * point is to have three layers, for requests, responses, and 825759Shsul@eecs.umich.edu * snoop responses respectively (snoop requests are instantaneous 835759Shsul@eecs.umich.edu * and do not need any flow control or arbitration). This case is 845759Shsul@eecs.umich.edu * similar to AHB and some OCP configurations. 855759Shsul@eecs.umich.edu * 8610318Sandreas.hansson@arm.com * As a further extensions beyond the three-layer bus, a future 875759Shsul@eecs.umich.edu * multi-layer bus has with one layer per connected slave port 885759Shsul@eecs.umich.edu * provides a full or partial crossbar, like AXI, OCP, PCIe etc. 895759Shsul@eecs.umich.edu * 905759Shsul@eecs.umich.edu * The template parameter, PortClass, indicates the destination 915759Shsul@eecs.umich.edu * port type for the bus. The retry list holds either master ports 925759Shsul@eecs.umich.edu * or slave ports, depending on the direction of the layer. Thus, 935759Shsul@eecs.umich.edu * a request layer has a retry list containing slave ports, 945759Shsul@eecs.umich.edu * whereas a response layer holds master ports. 955759Shsul@eecs.umich.edu */ 965759Shsul@eecs.umich.edu template <typename PortClass> 975759Shsul@eecs.umich.edu class Layer : public Drainable 985759Shsul@eecs.umich.edu { 995759Shsul@eecs.umich.edu 1005759Shsul@eecs.umich.edu public: 1015759Shsul@eecs.umich.edu 1025759Shsul@eecs.umich.edu /** 1035759Shsul@eecs.umich.edu * Create a bus layer and give it a name. The bus layer uses 1045759Shsul@eecs.umich.edu * the bus an event manager. 1056227Snate@binkert.org * 1065759Shsul@eecs.umich.edu * @param _bus the bus this layer belongs to 1075759Shsul@eecs.umich.edu * @param _name the layer's name 1085759Shsul@eecs.umich.edu * @param _clock clock period in ticks 1096227Snate@binkert.org */ 1105759Shsul@eecs.umich.edu Layer(BaseBus& _bus, const std::string& _name, Tick _clock); 1115759Shsul@eecs.umich.edu 1125759Shsul@eecs.umich.edu /** 1135759Shsul@eecs.umich.edu * Drain according to the normal semantics, so that the bus 11411320Ssteve.reinhardt@amd.com * can tell the layer to drain, and pass an event to signal 11511320Ssteve.reinhardt@amd.com * back when drained. 1165759Shsul@eecs.umich.edu * 11711320Ssteve.reinhardt@amd.com * @param de drain event to call once drained 1185759Shsul@eecs.umich.edu * 1195759Shsul@eecs.umich.edu * @return 1 if busy or waiting to retry, or 0 if idle 1205759Shsul@eecs.umich.edu */ 1215759Shsul@eecs.umich.edu unsigned int drain(DrainManager *dm); 1225759Shsul@eecs.umich.edu 1235759Shsul@eecs.umich.edu /** 1245759Shsul@eecs.umich.edu * Get the bus layer's name 1255759Shsul@eecs.umich.edu */ 1265759Shsul@eecs.umich.edu const std::string name() const { return bus.name() + _name; } 1275759Shsul@eecs.umich.edu 1285759Shsul@eecs.umich.edu 1298601Ssteve.reinhardt@amd.com /** 1305759Shsul@eecs.umich.edu * Determine if the bus layer accepts a packet from a specific 1315759Shsul@eecs.umich.edu * port. If not, the port in question is also added to the 1325759Shsul@eecs.umich.edu * retry list. In either case the state of the layer is updated 1335759Shsul@eecs.umich.edu * accordingly. 1345759Shsul@eecs.umich.edu * 1355759Shsul@eecs.umich.edu * @param port Source port resenting the packet 1365759Shsul@eecs.umich.edu * 1375759Shsul@eecs.umich.edu * @return True if the bus layer accepts the packet 1385759Shsul@eecs.umich.edu */ 1395759Shsul@eecs.umich.edu bool tryTiming(PortClass* port); 1405759Shsul@eecs.umich.edu 1415759Shsul@eecs.umich.edu /** 1425759Shsul@eecs.umich.edu * Deal with a destination port accepting a packet by potentially 1435759Shsul@eecs.umich.edu * removing the source port from the retry list (if retrying) and 1445759Shsul@eecs.umich.edu * occupying the bus layer accordingly. 1455759Shsul@eecs.umich.edu * 1465759Shsul@eecs.umich.edu * @param busy_time Time to spend as a result of a successful send 1478852Sandreas.hansson@arm.com */ 1485759Shsul@eecs.umich.edu void succeededTiming(Tick busy_time); 1495759Shsul@eecs.umich.edu 1505759Shsul@eecs.umich.edu /** 1515759Shsul@eecs.umich.edu * Deal with a destination port not accepting a packet by 1525759Shsul@eecs.umich.edu * potentially adding the source port to the retry list (if 1536227Snate@binkert.org * not already at the front) and occupying the bus layer 1548852Sandreas.hansson@arm.com * accordingly. 1555759Shsul@eecs.umich.edu * 1568852Sandreas.hansson@arm.com * @param busy_time Time to spend as a result of a failed send 1575759Shsul@eecs.umich.edu */ 1585759Shsul@eecs.umich.edu void failedTiming(PortClass* port, Tick busy_time); 1595759Shsul@eecs.umich.edu 1605759Shsul@eecs.umich.edu /** Occupy the bus layer until until */ 1615759Shsul@eecs.umich.edu void occupyLayer(Tick until); 1625958Sgblack@eecs.umich.edu 1635958Sgblack@eecs.umich.edu /** 1645759Shsul@eecs.umich.edu * Send a retry to the port at the head of the retryList. The 1655759Shsul@eecs.umich.edu * caller must ensure that the list is not empty. 1667720Sgblack@eecs.umich.edu */ 1675759Shsul@eecs.umich.edu void retryWaiting(); 1685759Shsul@eecs.umich.edu 1695759Shsul@eecs.umich.edu /** 1707532Ssteve.reinhardt@amd.com * Handler a retry from a neighbouring module. Eventually this 1712474SN/A * should be all encapsulated in the bus. This wraps 1726820SLisa.Hsu@amd.com * retryWaiting by verifying that there are ports waiting 1736820SLisa.Hsu@amd.com * before calling retryWaiting. 1747532Ssteve.reinhardt@amd.com */ 1756820SLisa.Hsu@amd.com void recvRetry(); 1765183Ssaidi@eecs.umich.edu 1777532Ssteve.reinhardt@amd.com private: 17810905Sandreas.sandberg@arm.com 1797532Ssteve.reinhardt@amd.com /** The bus this layer is a part of. */ 1807532Ssteve.reinhardt@amd.com BaseBus& bus; 1817532Ssteve.reinhardt@amd.com 1827532Ssteve.reinhardt@amd.com /** A name for this layer. */ 1837532Ssteve.reinhardt@amd.com std::string _name; 1847532Ssteve.reinhardt@amd.com 1857532Ssteve.reinhardt@amd.com /** 1867532Ssteve.reinhardt@amd.com * We declare an enum to track the state of the bus layer. The 1877532Ssteve.reinhardt@amd.com * starting point is an idle state where the bus layer is 1887532Ssteve.reinhardt@amd.com * waiting for a packet to arrive. Upon arrival, the bus layer 1897532Ssteve.reinhardt@amd.com * transitions to the busy state, where it remains either 1907532Ssteve.reinhardt@amd.com * until the packet transfer is done, or the header time is 1917532Ssteve.reinhardt@amd.com * spent. Once the bus layer leaves the busy state, it can 1927532Ssteve.reinhardt@amd.com * either go back to idle, if no packets have arrived while it 1937532Ssteve.reinhardt@amd.com * was busy, or the bus layer goes on to retry the first port 1947532Ssteve.reinhardt@amd.com * on the retryList. A similar transition takes place from 1955759Shsul@eecs.umich.edu * idle to retry if the bus layer receives a retry from one of 19610318Sandreas.hansson@arm.com * its connected ports. The retry state lasts until the port 1972474SN/A * in questions calls sendTiming and returns control to the 1987532Ssteve.reinhardt@amd.com * bus layer, or goes to a busy state if the port does not 1995713Shsul@eecs.umich.edu * immediately react to the retry by calling sendTiming. 2005713Shsul@eecs.umich.edu */ 2017701Sgblack@eecs.umich.edu enum State { IDLE, BUSY, RETRY }; 2027701Sgblack@eecs.umich.edu 2034997Sgblack@eecs.umich.edu /** track the state of the bus layer */ 2045713Shsul@eecs.umich.edu State state; 2052474SN/A 2062474SN/A /** the clock speed for the bus layer */ 2075958Sgblack@eecs.umich.edu Tick clock; 2086701Sgblack@eecs.umich.edu 2095958Sgblack@eecs.umich.edu /** manager to signal when drained */ 2105958Sgblack@eecs.umich.edu DrainManager *drainManager; 2116701Sgblack@eecs.umich.edu 2125958Sgblack@eecs.umich.edu /** 2135958Sgblack@eecs.umich.edu * An array of ports that retry should be called 2145958Sgblack@eecs.umich.edu * on because the original send failed for whatever reason. 2155958Sgblack@eecs.umich.edu */ 2165958Sgblack@eecs.umich.edu std::deque<PortClass*> retryList; 2175958Sgblack@eecs.umich.edu 2185958Sgblack@eecs.umich.edu /** 2195958Sgblack@eecs.umich.edu * Release the bus layer after being occupied and return to an 2205958Sgblack@eecs.umich.edu * idle state where we proceed to send a retry to any 2215958Sgblack@eecs.umich.edu * potential waiting port, or drain if asked to do so. 2225958Sgblack@eecs.umich.edu */ 22310223Ssteve.reinhardt@amd.com void releaseLayer(); 2245958Sgblack@eecs.umich.edu 2255958Sgblack@eecs.umich.edu /** event used to schedule a release of the layer */ 2265958Sgblack@eecs.umich.edu EventWrapper<Layer, &Layer::releaseLayer> releaseEvent; 2275958Sgblack@eecs.umich.edu 22810223Ssteve.reinhardt@amd.com }; 2295958Sgblack@eecs.umich.edu 2305958Sgblack@eecs.umich.edu /** cycles of overhead per transaction */ 23110223Ssteve.reinhardt@amd.com const Cycles headerCycles; 2325958Sgblack@eecs.umich.edu /** the width of the bus in bytes */ 2335958Sgblack@eecs.umich.edu const uint32_t width; 2345958Sgblack@eecs.umich.edu 23510223Ssteve.reinhardt@amd.com typedef AddrRangeMap<PortID>::iterator PortMapIter; 2365958Sgblack@eecs.umich.edu typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter; 2375958Sgblack@eecs.umich.edu AddrRangeMap<PortID> portMap; 238 239 AddrRange defaultRange; 240 241 /** 242 * Function called by the port when the bus is recieving a range change. 243 * 244 * @param master_port_id id of the port that received the change 245 */ 246 void recvRangeChange(PortID master_port_id); 247 248 /** Find which port connected to this bus (if any) should be given a packet 249 * with this address. 250 * @param addr Address to find port for. 251 * @return id of port that the packet should be sent out of. 252 */ 253 PortID findPort(Addr addr); 254 255 // Cache for the findPort function storing recently used ports from portMap 256 struct PortCache { 257 bool valid; 258 PortID id; 259 AddrRange range; 260 }; 261 262 PortCache portCache[3]; 263 264 // Checks the cache and returns the id of the port that has the requested 265 // address within its range 266 inline PortID checkPortCache(Addr addr) const { 267 if (portCache[0].valid && portCache[0].range == addr) { 268 return portCache[0].id; 269 } 270 if (portCache[1].valid && portCache[1].range == addr) { 271 return portCache[1].id; 272 } 273 if (portCache[2].valid && portCache[2].range == addr) { 274 return portCache[2].id; 275 } 276 277 return InvalidPortID; 278 } 279 280 // Clears the earliest entry of the cache and inserts a new port entry 281 inline void updatePortCache(short id, const AddrRange& range) { 282 portCache[2].valid = portCache[1].valid; 283 portCache[2].id = portCache[1].id; 284 portCache[2].range = portCache[1].range; 285 286 portCache[1].valid = portCache[0].valid; 287 portCache[1].id = portCache[0].id; 288 portCache[1].range = portCache[0].range; 289 290 portCache[0].valid = true; 291 portCache[0].id = id; 292 portCache[0].range = range; 293 } 294 295 // Clears the cache. Needs to be called in constructor. 296 inline void clearPortCache() { 297 portCache[2].valid = false; 298 portCache[1].valid = false; 299 portCache[0].valid = false; 300 } 301 302 /** 303 * Return the address ranges the bus is responsible for. 304 * 305 * @return a list of non-overlapping address ranges 306 */ 307 AddrRangeList getAddrRanges() const; 308 309 /** Calculate the timing parameters for the packet. Updates the 310 * firstWordTime and finishTime fields of the packet object. 311 * Returns the tick at which the packet header is completed (which 312 * will be all that is sent if the target rejects the packet). 313 */ 314 Tick calcPacketTiming(PacketPtr pkt); 315 316 /** 317 * Ask everyone on the bus what their size is and determine the 318 * bus size as either the maximum, or if no device specifies a 319 * block size return the default. 320 * 321 * @return the max of all the sizes or the default if none is set 322 */ 323 unsigned deviceBlockSize() const; 324 325 /** 326 * Remember for each of the master ports of the bus if we got an 327 * address range from the connected slave. For convenience, also 328 * keep track of if we got ranges from all the slave modules or 329 * not. 330 */ 331 std::vector<bool> gotAddrRanges; 332 bool gotAllAddrRanges; 333 334 /** The master and slave ports of the bus */ 335 std::vector<SlavePort*> slavePorts; 336 std::vector<MasterPort*> masterPorts; 337 338 /** Convenience typedefs. */ 339 typedef std::vector<SlavePort*>::iterator SlavePortIter; 340 typedef std::vector<MasterPort*>::iterator MasterPortIter; 341 typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter; 342 typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter; 343 344 /** Port that handles requests that don't match any of the interfaces.*/ 345 PortID defaultPortID; 346 347 /** If true, use address range provided by default device. Any 348 address not handled by another port and not in default device's 349 range will cause a fatal error. If false, just send all 350 addresses not handled by another port to default device. */ 351 const bool useDefaultRange; 352 353 uint32_t blockSize; 354 355 BaseBus(const BaseBusParams *p); 356 357 virtual ~BaseBus(); 358 359 public: 360 361 virtual void init(); 362 363 /** A function used to return the port associated with this bus object. */ 364 BaseMasterPort& getMasterPort(const std::string& if_name, 365 PortID idx = InvalidPortID); 366 BaseSlavePort& getSlavePort(const std::string& if_name, 367 PortID idx = InvalidPortID); 368 369 virtual unsigned int drain(DrainManager *dm) = 0; 370 371}; 372 373#endif //__MEM_BUS_HH__ 374