xbar.hh revision 9092 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Ali Saidi
42 *          Andreas Hansson
43 *          William Wang
44 */
45
46/**
47 * @file
48 * Declaration of an abstract bus base class.
49 */
50
51#ifndef __MEM_BUS_HH__
52#define __MEM_BUS_HH__
53
54#include <list>
55#include <set>
56
57#include "base/range.hh"
58#include "base/range_map.hh"
59#include "base/types.hh"
60#include "mem/mem_object.hh"
61#include "params/BaseBus.hh"
62
63/**
64 * The base bus contains the common elements of the non-coherent and
65 * coherent bus. It is an abstract class that does not have any of the
66 * functionality relating to the actual reception and transmission of
67 * packets, as this is left for the subclasses.
68 *
69 * The BaseBus is responsible for the basic flow control (busy or
70 * not), the administration of retries, and the address decoding.
71 */
72class BaseBus : public MemObject
73{
74
75  protected:
76
77    /**
78     * A bus layer is an internal bus structure with its own flow
79     * control and arbitration. Hence, a single-layer bus mimics a
80     * traditional off-chip tri-state bus (like PCI), where only one
81     * set of wires are shared. For on-chip buses, a good starting
82     * point is to have three layers, for requests, responses, and
83     * snoop responses respectively (snoop requests are instantaneous
84     * and do not need any flow control or arbitration). This case is
85     * similar to AHB and some OCP configurations. As a further
86     * extensions beyond the three-layer bus, a future multi-layer bus
87     * has with one layer per connected slave port provides a full or
88     * partial crossbar, like AXI, OCP, PCIe etc.
89     */
90    class Layer
91    {
92
93      public:
94
95        /**
96         * Create a bus layer and give it a name. The bus layer uses
97         * the bus an event manager.
98         *
99         * @param _bus the bus this layer belongs to
100         * @param _name the layer's name
101         * @param _clock clock period in ticks
102         */
103        Layer(BaseBus& _bus, const std::string& _name, Tick _clock);
104
105        /**
106         * Drain according to the normal semantics, so that the bus
107         * can tell the layer to drain, and pass an event to signal
108         * back when drained.
109         *
110         * @param de drain event to call once drained
111         *
112         * @return 1 if busy or waiting to retry, or 0 if idle
113         */
114        unsigned int drain(Event *de);
115
116        /**
117         * Get the bus layer's name
118         */
119        const std::string name() const { return bus.name() + _name; }
120
121
122        /**
123         * Determine if the bus layer accepts a packet from a specific
124         * port. If not, the port in question is also added to the
125         * retry list. In either case the state of the layer is updated
126         * accordingly.
127         *
128         * @param port Source port resenting the packet
129         *
130         * @return True if the bus layer accepts the packet
131         */
132        bool tryTiming(Port* port);
133
134        /**
135         * Deal with a destination port accepting a packet by potentially
136         * removing the source port from the retry list (if retrying) and
137         * occupying the bus layer accordingly.
138         *
139         * @param busy_time Time to spend as a result of a successful send
140         */
141        void succeededTiming(Tick busy_time);
142
143        /**
144         * Deal with a destination port not accepting a packet by
145         * potentially adding the source port to the retry list (if
146         * not already at the front) and occupying the bus layer
147         * accordingly.
148         *
149         * @param busy_time Time to spend as a result of a failed send
150         */
151        void failedTiming(SlavePort* port, Tick busy_time);
152
153        /** Occupy the bus layer until until */
154        void occupyLayer(Tick until);
155
156        /**
157         * Send a retry to the port at the head of the retryList. The
158         * caller must ensure that the list is not empty.
159         */
160        void retryWaiting();
161
162        /**
163         * Handler a retry from a neighbouring module. Eventually this
164         * should be all encapsulated in the bus. This wraps
165         * retryWaiting by verifying that there are ports waiting
166         * before calling retryWaiting.
167         */
168        void recvRetry();
169
170      private:
171
172        /** The bus this layer is a part of. */
173        BaseBus& bus;
174
175        /** A name for this layer. */
176        std::string _name;
177
178        /**
179         * We declare an enum to track the state of the bus layer. The
180         * starting point is an idle state where the bus layer is
181         * waiting for a packet to arrive. Upon arrival, the bus layer
182         * transitions to the busy state, where it remains either
183         * until the packet transfer is done, or the header time is
184         * spent. Once the bus layer leaves the busy state, it can
185         * either go back to idle, if no packets have arrived while it
186         * was busy, or the bus layer goes on to retry the first port
187         * on the retryList. A similar transition takes place from
188         * idle to retry if the bus layer receives a retry from one of
189         * its connected ports. The retry state lasts until the port
190         * in questions calls sendTiming and returns control to the
191         * bus layer, or goes to a busy state if the port does not
192         * immediately react to the retry by calling sendTiming.
193         */
194        enum State { IDLE, BUSY, RETRY };
195
196        /** track the state of the bus layer */
197        State state;
198
199        /** the clock speed for the bus layer */
200        Tick clock;
201
202        /** event for signalling when drained */
203        Event * drainEvent;
204
205        /**
206         * An array of pointers to ports that retry should be called
207         * on because the original send failed for whatever reason.
208         */
209        std::list<Port*> retryList;
210
211        /**
212         * Release the bus layer after being occupied and return to an
213         * idle state where we proceed to send a retry to any
214         * potential waiting port, or drain if asked to do so.
215         */
216        void releaseLayer();
217
218        /** event used to schedule a release of the layer */
219        EventWrapper<Layer, &Layer::releaseLayer> releaseEvent;
220
221    };
222
223    /** the clock speed for the bus */
224    Tick clock;
225    /** cycles of overhead per transaction */
226    int headerCycles;
227    /** the width of the bus in bytes */
228    int width;
229
230    typedef range_map<Addr, PortID>::iterator PortMapIter;
231    typedef range_map<Addr, PortID>::const_iterator PortMapConstIter;
232    range_map<Addr, PortID> portMap;
233
234    AddrRangeList defaultRange;
235
236    /**
237     * Function called by the port when the bus is recieving a range change.
238     *
239     * @param master_port_id id of the port that received the change
240     */
241    void recvRangeChange(PortID master_port_id);
242
243    /** Find which port connected to this bus (if any) should be given a packet
244     * with this address.
245     * @param addr Address to find port for.
246     * @return id of port that the packet should be sent out of.
247     */
248    PortID findPort(Addr addr);
249
250    // Cache for the findPort function storing recently used ports from portMap
251    struct PortCache {
252        bool valid;
253        PortID id;
254        Addr start;
255        Addr end;
256    };
257
258    PortCache portCache[3];
259
260    // Checks the cache and returns the id of the port that has the requested
261    // address within its range
262    inline PortID checkPortCache(Addr addr) {
263        if (portCache[0].valid && addr >= portCache[0].start &&
264            addr < portCache[0].end) {
265            return portCache[0].id;
266        }
267        if (portCache[1].valid && addr >= portCache[1].start &&
268                   addr < portCache[1].end) {
269            return portCache[1].id;
270        }
271        if (portCache[2].valid && addr >= portCache[2].start &&
272            addr < portCache[2].end) {
273            return portCache[2].id;
274        }
275
276        return InvalidPortID;
277    }
278
279    // Clears the earliest entry of the cache and inserts a new port entry
280    inline void updatePortCache(short id, Addr start, Addr end) {
281        portCache[2].valid = portCache[1].valid;
282        portCache[2].id    = portCache[1].id;
283        portCache[2].start = portCache[1].start;
284        portCache[2].end   = portCache[1].end;
285
286        portCache[1].valid = portCache[0].valid;
287        portCache[1].id    = portCache[0].id;
288        portCache[1].start = portCache[0].start;
289        portCache[1].end   = portCache[0].end;
290
291        portCache[0].valid = true;
292        portCache[0].id    = id;
293        portCache[0].start = start;
294        portCache[0].end   = end;
295    }
296
297    // Clears the cache. Needs to be called in constructor.
298    inline void clearPortCache() {
299        portCache[2].valid = false;
300        portCache[1].valid = false;
301        portCache[0].valid = false;
302    }
303
304    /**
305     * Return the address ranges the bus is responsible for.
306     *
307     * @return a list of non-overlapping address ranges
308     */
309    AddrRangeList getAddrRanges() const;
310
311    /** Calculate the timing parameters for the packet.  Updates the
312     * firstWordTime and finishTime fields of the packet object.
313     * Returns the tick at which the packet header is completed (which
314     * will be all that is sent if the target rejects the packet).
315     */
316    Tick calcPacketTiming(PacketPtr pkt);
317
318    /**
319     * Ask everyone on the bus what their size is
320     *
321     * @return the max of all the sizes
322     */
323    unsigned findBlockSize();
324
325    std::set<PortID> inRecvRangeChange;
326
327    /** The master and slave ports of the bus */
328    std::vector<SlavePort*> slavePorts;
329    std::vector<MasterPort*> masterPorts;
330
331    /** Convenience typedefs. */
332    typedef std::vector<SlavePort*>::iterator SlavePortIter;
333    typedef std::vector<MasterPort*>::iterator MasterPortIter;
334    typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter;
335    typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter;
336
337    /** Port that handles requests that don't match any of the interfaces.*/
338    PortID defaultPortID;
339
340    /** If true, use address range provided by default device.  Any
341       address not handled by another port and not in default device's
342       range will cause a fatal error.  If false, just send all
343       addresses not handled by another port to default device. */
344    bool useDefaultRange;
345
346    unsigned defaultBlockSize;
347    unsigned cachedBlockSize;
348    bool cachedBlockSizeValid;
349
350    BaseBus(const BaseBusParams *p);
351
352    virtual ~BaseBus();
353
354  public:
355
356    /** A function used to return the port associated with this bus object. */
357    virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1);
358    virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
359
360    virtual unsigned int drain(Event *de) = 0;
361
362};
363
364#endif //__MEM_BUS_HH__
365