tport.cc revision 9662 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Andreas Hansson
42 */
43
44#include "mem/mem_object.hh"
45#include "mem/tport.hh"
46
47SimpleTimingPort::SimpleTimingPort(const std::string& _name,
48                                   MemObject* _owner) :
49    QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
50{
51}
52
53void
54SimpleTimingPort::recvFunctional(PacketPtr pkt)
55{
56    if (!queue.checkFunctional(pkt)) {
57        // do an atomic access and throw away the returned latency
58        recvAtomic(pkt);
59    }
60}
61
62bool
63SimpleTimingPort::recvTimingReq(PacketPtr pkt)
64{
65    /// @todo temporary hack to deal with memory corruption issue until
66    /// 4-phase transactions are complete. Remove me later
67    for (int x = 0; x < pendingDelete.size(); x++)
68        delete pendingDelete[x];
69    pendingDelete.clear();
70
71    // the SimpleTimingPort should not be used anywhere where there is
72    // a need to deal with inhibited packets
73    if (pkt->memInhibitAsserted())
74        panic("SimpleTimingPort should never see an inhibited request\n");
75
76    bool needsResponse = pkt->needsResponse();
77    Tick latency = recvAtomic(pkt);
78    // turn packet around to go back to requester if response expected
79    if (needsResponse) {
80        // recvAtomic() should already have turned packet into
81        // atomic response
82        assert(pkt->isResponse());
83        schedTimingResp(pkt, curTick() + latency);
84    } else {
85        /// @todo nominally we should just delete the packet here.
86        /// Until 4-phase stuff we can't because the sending
87        /// cache is still relying on it
88        pendingDelete.push_back(pkt);
89    }
90
91    return true;
92}
93