simple_mem.hh revision 9349:844f9e724343 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Andreas Hansson
42 */
43
44/**
45 * @file
46 * SimpleMemory declaration
47 */
48
49#ifndef __SIMPLE_MEMORY_HH__
50#define __SIMPLE_MEMORY_HH__
51
52#include "mem/abstract_mem.hh"
53#include "mem/tport.hh"
54#include "params/SimpleMemory.hh"
55
56/**
57 * The simple memory is a basic single-ported memory controller with
58 * an configurable throughput and latency, potentially with a variance
59 * added to the latter. It uses a QueueSlavePort to avoid dealing with
60 * the flow control of sending responses.
61 * @sa  \ref gem5MemorySystem "gem5 Memory System"
62 */
63class SimpleMemory : public AbstractMemory
64{
65
66  private:
67
68    class MemoryPort : public QueuedSlavePort
69    {
70
71      private:
72
73        /// Queue holding the response packets
74        SlavePacketQueue queueImpl;
75        SimpleMemory& memory;
76
77      public:
78
79        MemoryPort(const std::string& _name, SimpleMemory& _memory);
80
81      protected:
82
83        Tick recvAtomic(PacketPtr pkt);
84
85        void recvFunctional(PacketPtr pkt);
86
87        bool recvTimingReq(PacketPtr pkt);
88
89        AddrRangeList getAddrRanges() const;
90
91    };
92
93    MemoryPort port;
94
95    Tick lat;
96    Tick lat_var;
97
98    /// Bandwidth in ticks per byte
99    const double bandwidth;
100
101    /**
102     * Track the state of the memory as either idle or busy, no need
103     * for an enum with only two states.
104     */
105    bool isBusy;
106
107    /**
108     * Remember if we have to retry an outstanding request that
109     * arrived while we were busy.
110     */
111    bool retryReq;
112
113    /**
114     * Release the memory after being busy and send a retry if a
115     * request was rejected in the meanwhile.
116     */
117    void release();
118
119    EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
120
121    /** @todo this is a temporary workaround until the 4-phase code is
122     * committed. upstream caches needs this packet until true is returned, so
123     * hold onto it for deletion until a subsequent call
124     */
125    std::vector<PacketPtr> pendingDelete;
126
127  public:
128
129    SimpleMemory(const SimpleMemoryParams *p);
130    virtual ~SimpleMemory() { }
131
132    unsigned int drain(DrainManager *dm);
133
134    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
135                                        PortID idx = InvalidPortID);
136    virtual void init();
137
138  protected:
139
140    Tick doAtomicAccess(PacketPtr pkt);
141    void doFunctionalAccess(PacketPtr pkt);
142    bool recvTimingReq(PacketPtr pkt);
143    Tick calculateLatency(PacketPtr pkt);
144
145};
146
147#endif //__SIMPLE_MEMORY_HH__
148