simple_mem.hh revision 9228:bbdca4088834 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Andreas Hansson
42 */
43
44/**
45 * @file
46 * SimpleMemory declaration
47 */
48
49#ifndef __SIMPLE_MEMORY_HH__
50#define __SIMPLE_MEMORY_HH__
51
52#include "mem/abstract_mem.hh"
53#include "mem/tport.hh"
54#include "params/SimpleMemory.hh"
55
56/**
57 * The simple memory is a basic single-ported memory controller with
58 * an configurable throughput and latency, potentially with a variance
59 * added to the latter. It uses a QueueSlavePort to avoid dealing with
60 * the flow control of sending responses.
61 */
62class SimpleMemory : public AbstractMemory
63{
64
65  private:
66
67    class MemoryPort : public QueuedSlavePort
68    {
69
70      private:
71
72        /// Queue holding the response packets
73        SlavePacketQueue queueImpl;
74        SimpleMemory& memory;
75
76      public:
77
78        MemoryPort(const std::string& _name, SimpleMemory& _memory);
79
80      protected:
81
82        Tick recvAtomic(PacketPtr pkt);
83
84        void recvFunctional(PacketPtr pkt);
85
86        bool recvTimingReq(PacketPtr pkt);
87
88        AddrRangeList getAddrRanges() const;
89
90    };
91
92    MemoryPort port;
93
94    Tick lat;
95    Tick lat_var;
96
97    /// Bandwidth in ticks per byte
98    const double bandwidth;
99
100    /**
101     * Track the state of the memory as either idle or busy, no need
102     * for an enum with only two states.
103     */
104    bool isBusy;
105
106    /**
107     * Remember if we have to retry an outstanding request that
108     * arrived while we were busy.
109     */
110    bool retryReq;
111
112    /**
113     * Release the memory after being busy and send a retry if a
114     * request was rejected in the meanwhile.
115     */
116    void release();
117
118    EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
119
120  public:
121
122    SimpleMemory(const SimpleMemoryParams *p);
123    virtual ~SimpleMemory() { }
124
125    unsigned int drain(Event* de);
126
127    virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
128    virtual void init();
129
130  protected:
131
132    Tick doAtomicAccess(PacketPtr pkt);
133    void doFunctionalAccess(PacketPtr pkt);
134    bool recvTimingReq(PacketPtr pkt);
135    Tick calculateLatency(PacketPtr pkt);
136
137};
138
139#endif //__SIMPLE_MEMORY_HH__
140