serial_link.hh revision 11185:0ff78be3bc67
12SN/A/* 22190SN/A * Copyright (c) 2011-2013 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152SN/A * Copyright (c) 2015 The University of Bologna 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272665SN/A * this software without specific prior written permission. 282665SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312680Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322680Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346329Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353453Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366216Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371858SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386658Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392423SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406216Snate@binkert.org * 412190SN/A * Authors: Ali Saidi 42217SN/A * Steve Reinhardt 432SN/A * Andreas Hansson 442190SN/A * Erfan Azarkhish 452190SN/A */ 463453Sgblack@eecs.umich.edu 473453Sgblack@eecs.umich.edu/** 486022Sgblack@eecs.umich.edu * @file 493453Sgblack@eecs.umich.edu * Declaration of the SerialLink Class, modeling Hybrid-Memory-Cube's serial 502190SN/A * interface. 512313SN/A */ 522235SN/A 532423SN/A#ifndef __MEM_SERIAL_LINK_HH__ 542521SN/A#define __MEM_SERIAL_LINK_HH__ 552521SN/A 562190SN/A#include <deque> 572190SN/A 583548Sgblack@eecs.umich.edu#include "base/types.hh" 593548Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 603548Sgblack@eecs.umich.edu#include "params/SerialLink.hh" 613548Sgblack@eecs.umich.edu 622330SN/A/** 632SN/A * SerialLink is a simple variation of the Bridge class, with the ability to 642680Sktlim@umich.edu * account for the latency of packet serialization. We assume that the 652680Sktlim@umich.edu * serializer component at the transmitter side does not need to receive the 662680Sktlim@umich.edu * whole packet to start the serialization. But the deserializer waits for the 672680Sktlim@umich.edu * complete packet to check its integrity first. 682680Sktlim@umich.edu */ 692680Sktlim@umich.educlass SerialLink : public MemObject 702680Sktlim@umich.edu{ 712680Sktlim@umich.edu protected: 722680Sktlim@umich.edu 732680Sktlim@umich.edu /** 742680Sktlim@umich.edu * A deferred packet stores a packet along with its scheduled 752682Sktlim@umich.edu * transmission time 762680Sktlim@umich.edu */ 772680Sktlim@umich.edu class DeferredPacket 782680Sktlim@umich.edu { 792680Sktlim@umich.edu 802680Sktlim@umich.edu public: 812SN/A 822107SN/A const Tick tick; 832107SN/A const PacketPtr pkt; 842190SN/A 852455SN/A DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) 862455SN/A { } 872159SN/A }; 882SN/A 896029Ssteve.reinhardt@amd.com // Forward declaration to allow the slave port to have a pointer 90246SN/A class SerialLinkMasterPort; 91246SN/A 92246SN/A /** 93246SN/A * The port on the side that receives requests and sends 94246SN/A * responses. The slave port has a set of address ranges that it 95246SN/A * is responsible for. The slave port also has a buffer for the 96246SN/A * responses not yet sent. 972190SN/A */ 98246SN/A class SerialLinkSlavePort : public SlavePort 99246SN/A { 100246SN/A 101246SN/A private: 102246SN/A 103246SN/A /** The serial_link to which this port belongs. */ 104246SN/A SerialLink& serial_link; 1052SN/A 1062680Sktlim@umich.edu /** 1072423SN/A * Master port on the other side of the serial_link. 1082190SN/A */ 109180SN/A SerialLinkMasterPort& masterPort; 1105712Shsul@eecs.umich.edu 1112190SN/A /** Minimum request delay though this serial_link. */ 1125715Shsul@eecs.umich.edu const Cycles delay; 1135715Shsul@eecs.umich.edu 1145715Shsul@eecs.umich.edu /** Address ranges to pass through the serial_link */ 1155714Shsul@eecs.umich.edu const AddrRangeList ranges; 1165714Shsul@eecs.umich.edu 1175714Shsul@eecs.umich.edu /** 1185714Shsul@eecs.umich.edu * Response packet queue. Response packets are held in this 1195714Shsul@eecs.umich.edu * queue for a specified delay to model the processing delay 1206022Sgblack@eecs.umich.edu * of the serial_link. We use a deque as we need to iterate over 1212190SN/A * the items for functional accesses. 1226022Sgblack@eecs.umich.edu */ 1232521SN/A std::deque<DeferredPacket> transmitList; 1244997Sgblack@eecs.umich.edu 1254997Sgblack@eecs.umich.edu /** Counter to track the outstanding responses. */ 1265803Snate@binkert.org unsigned int outstandingResponses; 1273548Sgblack@eecs.umich.edu 1282654SN/A /** If we should send a retry when space becomes available. */ 1292521SN/A bool retryReq; 1302521SN/A 1315499Ssaidi@eecs.umich.edu /** Max queue size for reserved responses. */ 1323673Srdreslin@umich.edu unsigned int respQueueLimit; 1335497Ssaidi@eecs.umich.edu 1342190SN/A /** 1352518SN/A * Is this side blocked from accepting new response packets. 1362518SN/A * 1372190SN/A * @return true if the reserved space has reached the set limit 1382190SN/A */ 1392190SN/A bool respQueueFull() const; 1402190SN/A 1412159SN/A /** 1422235SN/A * Handle send event, scheduled when the packet at the head of 1432103SN/A * the response queue is ready to transmit (for timing 144393SN/A * accesses only). 145393SN/A */ 1462190SN/A void trySendTiming(); 147393SN/A 148393SN/A /** Send event for the response queue. */ 1495250Sksewell@umich.edu EventWrapper<SerialLinkSlavePort, 150393SN/A &SerialLinkSlavePort::trySendTiming> sendEvent; 151393SN/A 1525250Sksewell@umich.edu public: 1532159SN/A 1542159SN/A /** 1552190SN/A * Constructor for the SerialLinkSlavePort. 1562159SN/A * 1572159SN/A * @param _name the port name including the owner 1582680Sktlim@umich.edu * @param _serial_link the structural owner 1592159SN/A * @param _masterPort the master port on the other side of the 1602190SN/A * serial_link 1612159SN/A * @param _delay the delay in cycles from receiving to sending 1622190SN/A * @param _resp_limit the size of the response queue 1632190SN/A * @param _ranges a number of address ranges to forward 1642159SN/A */ 1652235SN/A SerialLinkSlavePort(const std::string& _name, SerialLink& 1662313SN/A _serial_link, SerialLinkMasterPort& _masterPort, 1672235SN/A Cycles _delay, int _resp_limit, const 1682235SN/A std::vector<AddrRange>& _ranges); 1692235SN/A 1702235SN/A /** 1712235SN/A * Queue a response packet to be sent out later and also schedule 1722254SN/A * a send if necessary. 1732254SN/A * 1742254SN/A * @param pkt a response to send out after a delay 1752235SN/A * @param when tick when response packet should be sent 1762235SN/A */ 1772235SN/A void schedTimingResp(PacketPtr pkt, Tick when); 1782254SN/A 1792190SN/A /** 1802159SN/A * Retry any stalled request that we have failed to accept at 1812680Sktlim@umich.edu * an earlier point in time. This call will do nothing if no 1822159SN/A * request is waiting. 1832190SN/A */ 1842159SN/A void retryStalledReq(); 1852159SN/A 1862159SN/A protected: 1872159SN/A 1882190SN/A /** When receiving a timing request from the peer port, 1892159SN/A pass it to the serial_link. */ 1902455SN/A bool recvTimingReq(PacketPtr pkt); 1912159SN/A 1922455SN/A /** When receiving a retry request from the peer port, 1932159SN/A pass it to the serial_link. */ 1942190SN/A void recvRespRetry(); 1952159SN/A 1962455SN/A /** When receiving a Atomic requestfrom the peer port, 1972159SN/A pass it to the serial_link. */ 1982455SN/A Tick recvAtomic(PacketPtr pkt); 1992455SN/A 2002190SN/A /** When receiving a Functional request from the peer port, 2012159SN/A pass it to the serial_link. */ 2022190SN/A void recvFunctional(PacketPtr pkt); 2032159SN/A 2042190SN/A /** When receiving a address range request the peer port, 2052159SN/A pass it to the serial_link. */ 2062190SN/A AddrRangeList getAddrRanges() const; 2072159SN/A }; 2082447SN/A 2092447SN/A 2102447SN/A /** 2112447SN/A * Port on the side that forwards requests and receives 2125260Sksewell@umich.edu * responses. The master port has a buffer for the requests not 2135260Sksewell@umich.edu * yet sent. 2145260Sksewell@umich.edu */ 2155260Sksewell@umich.edu class SerialLinkMasterPort : public MasterPort 2165260Sksewell@umich.edu { 2175260Sksewell@umich.edu 2185260Sksewell@umich.edu private: 2195260Sksewell@umich.edu 2204172Ssaidi@eecs.umich.edu /** The serial_link to which this port belongs. */ 2214172Ssaidi@eecs.umich.edu SerialLink& serial_link; 2222190SN/A 2232159SN/A /** 2244172Ssaidi@eecs.umich.edu * The slave port on the other side of the serial_link. 2252190SN/A */ 2263468Sgblack@eecs.umich.edu SerialLinkSlavePort& slavePort; 2272190SN/A 2286313Sgblack@eecs.umich.edu /** Minimum delay though this serial_link. */ 2296313Sgblack@eecs.umich.edu const Cycles delay; 2306313Sgblack@eecs.umich.edu 2316221Snate@binkert.org /** 2326221Snate@binkert.org * Request packet queue. Request packets are held in this 2336221Snate@binkert.org * queue for a specified delay to model the processing delay 2346221Snate@binkert.org * of the serial_link. We use a deque as we need to iterate over 2356221Snate@binkert.org * the items for functional accesses. 2364661Sksewell@umich.edu */ 2376221Snate@binkert.org std::deque<DeferredPacket> transmitList; 2386221Snate@binkert.org 2396221Snate@binkert.org /** Max queue size for request packets */ 2406221Snate@binkert.org const unsigned int reqQueueLimit; 2414661Sksewell@umich.edu 2422235SN/A /** 2432235SN/A * Handle send event, scheduled when the packet at the head of 2442190SN/A * the outbound queue is ready to transmit (for timing 2452190SN/A * accesses only). 2462190SN/A */ 2472159SN/A void trySendTiming(); 2482235SN/A 2492190SN/A /** Send event for the request queue. */ 2502190SN/A EventWrapper<SerialLinkMasterPort, 2512159SN/A &SerialLinkMasterPort::trySendTiming> sendEvent; 2522235SN/A 2532190SN/A public: 2542834Sksewell@umich.edu 2554111Sgblack@eecs.umich.edu /** 2564111Sgblack@eecs.umich.edu * Constructor for the SerialLinkMasterPort. 2572834Sksewell@umich.edu * 2582834Sksewell@umich.edu * @param _name the port name including the owner 2592834Sksewell@umich.edu * @param _serial_link the structural owner 2602834Sksewell@umich.edu * @param _slavePort the slave port on the other side of the 2612159SN/A * serial_link 2622525SN/A * @param _delay the delay in cycles from receiving to sending 2635217Ssaidi@eecs.umich.edu * @param _req_limit the size of the request queue 2645217Ssaidi@eecs.umich.edu */ 2652159SN/A SerialLinkMasterPort(const std::string& _name, SerialLink& 2662159SN/A _serial_link, SerialLinkSlavePort& _slavePort, Cycles 2672682Sktlim@umich.edu _delay, int _req_limit); 2682682Sktlim@umich.edu 2692682Sktlim@umich.edu /** 2702682Sktlim@umich.edu * Is this side blocked from accepting new request packets. 2712682Sktlim@umich.edu * 2722682Sktlim@umich.edu * @return true if the occupied space has reached the set limit 2732682Sktlim@umich.edu */ 2742682Sktlim@umich.edu bool reqQueueFull() const; 2752682Sktlim@umich.edu 2762682Sktlim@umich.edu /** 2772680Sktlim@umich.edu * Queue a request packet to be sent out later and also schedule 2782680Sktlim@umich.edu * a send if necessary. 2792190SN/A * 2802190SN/A * @param pkt a request to send out after a delay 2812680Sktlim@umich.edu * @param when tick when response packet should be sent 2822680Sktlim@umich.edu */ 2832159SN/A void schedTimingReq(PacketPtr pkt, Tick when); 2842190SN/A 2852680Sktlim@umich.edu /** 2862SN/A * Check a functional request against the packets in our 2872SN/A * request queue. 2882SN/A * 2892680Sktlim@umich.edu * @param pkt packet to check against 2902SN/A * 2915712Shsul@eecs.umich.edu * @return true if we find a match 2922SN/A */ 2935715Shsul@eecs.umich.edu bool checkFunctional(PacketPtr pkt); 2945715Shsul@eecs.umich.edu 2955715Shsul@eecs.umich.edu protected: 2965714Shsul@eecs.umich.edu 2975714Shsul@eecs.umich.edu /** When receiving a timing request from the peer port, 2985714Shsul@eecs.umich.edu pass it to the serial_link. */ 2995714Shsul@eecs.umich.edu bool recvTimingResp(PacketPtr pkt); 3005714Shsul@eecs.umich.edu 3016022Sgblack@eecs.umich.edu /** When receiving a retry request from the peer port, 3021917SN/A pass it to the serial_link. */ 3036022Sgblack@eecs.umich.edu void recvReqRetry(); 3042521SN/A }; 3054997Sgblack@eecs.umich.edu 3064997Sgblack@eecs.umich.edu /** Slave port of the serial_link. */ 3075803Snate@binkert.org SerialLinkSlavePort slavePort; 3083548Sgblack@eecs.umich.edu 3093548Sgblack@eecs.umich.edu /** Master port of the serial_link. */ 3102654SN/A SerialLinkMasterPort masterPort; 3112680Sktlim@umich.edu 3122521SN/A /** Number of parallel lanes in this serial link */ 3135499Ssaidi@eecs.umich.edu unsigned num_lanes; 3143673Srdreslin@umich.edu 3155497Ssaidi@eecs.umich.edu public: 3162SN/A 3172680Sktlim@umich.edu virtual BaseMasterPort& getMasterPort(const std::string& if_name, 3182518SN/A PortID idx = InvalidPortID); 3192680Sktlim@umich.edu virtual BaseSlavePort& getSlavePort(const std::string& if_name, 3202SN/A PortID idx = InvalidPortID); 3212SN/A 3222680Sktlim@umich.edu virtual void init(); 323595SN/A 3242680Sktlim@umich.edu typedef SerialLinkParams Params; 3252SN/A 3262190SN/A SerialLink(SerialLinkParams *p); 3272190SN/A}; 3282680Sktlim@umich.edu 3292SN/A#endif //__MEM_SERIAL_LINK_HH__ 3302190SN/A