secure_port_proxy.hh revision 14007:36f842f523c6
1/* 2 * Copyright (c) 2011-2013, 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 */ 39 40/** 41 * @file 42 * PortProxy Object Declaration. 43 * 44 * Port proxies are used when non-structural entities need access to 45 * the memory system (or structural entities that want to peak into 46 * the memory system without making a real memory access). 47 * 48 * Proxy objects replace the previous FunctionalPort, TranslatingPort 49 * and VirtualPort objects, which provided the same functionality as 50 * the proxies, but were instances of ports not corresponding to real 51 * structural ports of the simulated system. Via the port proxies all 52 * the accesses go through an actual port (either the system port, 53 * e.g. for processes or initialisation, or a the data port of the 54 * CPU, e.g. for threads) and thus are transparent to a potentially 55 * distributed memory and automatically adhere to the memory map of 56 * the system. 57 */ 58 59#ifndef __MEM_SECURE_PORT_PROXY_HH__ 60#define __MEM_SECURE_PORT_PROXY_HH__ 61 62#include "mem/port_proxy.hh" 63 64/** 65 * This object is a proxy for a structural port, to be used for debug 66 * accesses to secure memory. 67 * 68 * The addresses are interpreted as physical addresses to secure memory. 69 */ 70class SecurePortProxy : public PortProxy 71{ 72 public: 73 SecurePortProxy(MasterPort &port, unsigned int cache_line_size) 74 : PortProxy(port, cache_line_size) {} 75 76 void readBlob(Addr addr, uint8_t *p, int size) const override; 77 void writeBlob(Addr addr, const uint8_t *p, int size) const override; 78 void memsetBlob(Addr addr, uint8_t val, int size) const override; 79}; 80 81#endif // __MEM_SECURE_PORT_PROXY_HH__ 82