se_translating_port_proxy.cc revision 14196:ce364f5517f3
11689SN/A/*
22329SN/A * Copyright (c) 2011 ARM Limited
31689SN/A * All rights reserved
41689SN/A *
51689SN/A * The license below extends only to copyright in the software and shall
61689SN/A * not be construed as granting a license to any other intellectual
71689SN/A * property including but not limited to intellectual property relating
81689SN/A * to a hardware implementation of the functionality of the software
91689SN/A * licensed hereunder.  You may use the software subject to the license
101689SN/A * terms below provided that you ensure that this notice is replicated
111689SN/A * unmodified and in its entirety in all distributions of the software,
121689SN/A * modified or unmodified, in source code or in binary form.
131689SN/A *
141689SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292831Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
321858SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
331717SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352980Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
371061SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392980Sgblack@eecs.umich.edu *
402292SN/A * Authors: Ron Dreslinski
411060SN/A *          Steve Reinhardt
421060SN/A *          Andreas Hansson
431060SN/A */
442292SN/A
451060SN/A#include "mem/se_translating_port_proxy.hh"
462292SN/A
472877Sksewell@umich.edu#include <string>
482292SN/A
492292SN/A#include "arch/isa_traits.hh"
502292SN/A#include "base/chunk_generator.hh"
512292SN/A#include "config/the_isa.hh"
522980Sgblack@eecs.umich.edu#include "mem/page_table.hh"
532292SN/A#include "sim/process.hh"
542292SN/A#include "sim/system.hh"
552292SN/A
562292SN/Ausing namespace TheISA;
572292SN/A
582292SN/ASETranslatingPortProxy::SETranslatingPortProxy(
592292SN/A        SendFunctionalFunc func, Process *p, AllocType alloc)
602292SN/A    : PortProxy(func, p->system->cacheLineSize()), pTable(p->pTable),
612292SN/A      process(p), allocating(alloc)
622292SN/A{ }
632292SN/ASETranslatingPortProxy::SETranslatingPortProxy(MasterPort &port,
642292SN/A                                               Process *p, AllocType alloc)
652292SN/A    : PortProxy(port, p->system->cacheLineSize()), pTable(p->pTable),
662292SN/A      process(p), allocating(alloc)
672292SN/A{ }
682292SN/A
692292SN/Abool
702292SN/ASETranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
712292SN/A{
722292SN/A    int prevSize = 0;
732292SN/A    auto *bytes = static_cast<uint8_t *>(p);
742292SN/A
752292SN/A    for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
762292SN/A        Addr paddr;
772292SN/A
782292SN/A        if (!pTable->translate(gen.addr(),paddr))
792292SN/A            return false;
802292SN/A
812292SN/A        PortProxy::readBlobPhys(paddr, 0, bytes + prevSize, gen.size());
822292SN/A        prevSize += gen.size();
832292SN/A    }
842292SN/A
852292SN/A    return true;
862292SN/A}
872292SN/A
882292SN/A
892292SN/Abool
902292SN/ASETranslatingPortProxy::tryWriteBlob(Addr addr, const void *p, int size) const
912292SN/A{
922292SN/A    int prevSize = 0;
932292SN/A    auto *bytes = static_cast<const uint8_t *>(p);
942292SN/A
952292SN/A    for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
962292SN/A        Addr paddr;
972292SN/A
982292SN/A        if (!pTable->translate(gen.addr(), paddr)) {
992292SN/A            if (allocating == Always) {
1001060SN/A                process->allocateMem(roundDown(gen.addr(), PageBytes),
1011060SN/A                                     PageBytes);
1021061SN/A            } else if (allocating == NextPage) {
1031060SN/A                // check if we've accessed the next page on the stack
1042733Sktlim@umich.edu                if (!process->fixupStackFault(gen.addr()))
1051060SN/A                    panic("Page table fault when accessing virtual address %#x "
1061060SN/A                            "during functional write\n", gen.addr());
1071060SN/A            } else {
1082292SN/A                return false;
1092292SN/A            }
1102292SN/A            pTable->translate(gen.addr(), paddr);
1112292SN/A        }
1121060SN/A
1132292SN/A        PortProxy::writeBlobPhys(paddr, 0, bytes + prevSize, gen.size());
1142292SN/A        prevSize += gen.size();
1152292SN/A    }
1162292SN/A
1172292SN/A    return true;
1182292SN/A}
1192292SN/A
1202292SN/A
1212980Sgblack@eecs.umich.edubool
1222292SN/ASETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const
1232292SN/A{
1242292SN/A    for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
1252292SN/A        Addr paddr;
1262292SN/A
1272307SN/A        if (!pTable->translate(gen.addr(), paddr)) {
1282307SN/A            if (allocating == Always) {
1292307SN/A                process->allocateMem(roundDown(gen.addr(), PageBytes),
1302307SN/A                                     PageBytes);
1312307SN/A                pTable->translate(gen.addr(), paddr);
1322307SN/A            } else {
1332307SN/A                return false;
1342307SN/A            }
1352307SN/A        }
1362307SN/A
1372307SN/A        PortProxy::memsetBlobPhys(paddr, 0, val, gen.size());
1382307SN/A    }
1392307SN/A
1402307SN/A    return true;
1412307SN/A}
1422307SN/A