Sequencer.py revision 8839
16821SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 28166SLisa.Hsu@amd.com# All rights reserved. 36821SN/A# 46821SN/A# Redistribution and use in source and binary forms, with or without 56821SN/A# modification, are permitted provided that the following conditions are 66821SN/A# met: redistributions of source code must retain the above copyright 76821SN/A# notice, this list of conditions and the following disclaimer; 86821SN/A# redistributions in binary form must reproduce the above copyright 96821SN/A# notice, this list of conditions and the following disclaimer in the 106821SN/A# documentation and/or other materials provided with the distribution; 116821SN/A# neither the name of the copyright holders nor the names of its 126821SN/A# contributors may be used to endorse or promote products derived from 136821SN/A# this software without specific prior written permission. 146821SN/A# 156821SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166821SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176821SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186821SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196821SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206821SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216821SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226821SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236821SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246821SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256821SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266821SN/A# 276821SN/A# Authors: Steve Reinhardt 286821SN/A# Brad Beckmann 296818SN/A 306818SN/Afrom m5.params import * 316818SN/Afrom m5.proxy import * 326818SN/Afrom MemObject import MemObject 336818SN/A 346818SN/Aclass RubyPort(MemObject): 356818SN/A type = 'RubyPort' 366818SN/A abstract = True 376818SN/A slave = VectorSlavePort("CPU slave port") 386818SN/A master = VectorMasterPort("CPU master port") 396818SN/A version = Param.Int(0, "") 406818SN/A pio_port = MasterPort("Ruby_pio_port") 416818SN/A physmem = Param.PhysicalMemory("") 426818SN/A physMemPort = MasterPort("port to physical memory") 436818SN/A using_ruby_tester = Param.Bool(False, "") 446818SN/A using_network_tester = Param.Bool(False, "") 456818SN/A access_phys_mem = Param.Bool(True, 466818SN/A "should the rubyport atomically update phys_mem") 476818SN/A ruby_system = Param.RubySystem("") 486818SN/A 496818SN/Aclass RubyPortProxy(RubyPort): 506818SN/A type = 'RubyPortProxy' 516818SN/A 526818SN/Aclass RubySequencer(RubyPort): 536818SN/A type = 'RubySequencer' 546818SN/A cxx_class = 'Sequencer' 556818SN/A icache = Param.RubyCache("") 566818SN/A dcache = Param.RubyCache("") 576818SN/A max_outstanding_requests = Param.Int(16, 586818SN/A "max requests (incl. prefetches) outstanding") 596818SN/A deadlock_threshold = Param.Int(500000, 606818SN/A "max outstanding cycles for a request before deadlock/livelock declared") 616818SN/A 626818SN/Aclass DMASequencer(RubyPort): 636818SN/A type = 'DMASequencer' 646818SN/A