Sequencer.py revision 7019:a49fd5febdce
19243SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc.
211675Swendy.elsasser@arm.com# All rights reserved.
39243SN/A#
49243SN/A# Redistribution and use in source and binary forms, with or without
59243SN/A# modification, are permitted provided that the following conditions are
69243SN/A# met: redistributions of source code must retain the above copyright
79243SN/A# notice, this list of conditions and the following disclaimer;
89243SN/A# redistributions in binary form must reproduce the above copyright
99243SN/A# notice, this list of conditions and the following disclaimer in the
109243SN/A# documentation and/or other materials provided with the distribution;
119243SN/A# neither the name of the copyright holders nor the names of its
129243SN/A# contributors may be used to endorse or promote products derived from
139243SN/A# this software without specific prior written permission.
149831SN/A#
159831SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
169831SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
179243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
189243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
199243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
209243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
219243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
229243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
239243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
249243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
259243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
269243SN/A#
279243SN/A# Authors: Steve Reinhardt
289243SN/A#          Brad Beckmann
299243SN/A
309243SN/Afrom m5.params import *
319243SN/Afrom m5.proxy import *
329243SN/Afrom MemObject import MemObject
339243SN/A
349243SN/Aclass RubyPort(MemObject):
359243SN/A    type = 'RubyPort'
369243SN/A    abstract = True
379243SN/A    port = VectorPort("M5 port")
389243SN/A    version = Param.Int(0, "")
399243SN/A    pio_port = Port("Ruby_pio_port")
409243SN/A    physmem = Param.PhysicalMemory("")
419243SN/A    physMemPort = Port("port to physical memory")
429967SN/A
4310618SOmar.Naji@arm.comclass RubySequencer(RubyPort):
4411678Swendy.elsasser@arm.com    type = 'RubySequencer'
459243SN/A    cxx_class = 'Sequencer'
469243SN/A    icache = Param.RubyCache("")
4711793Sbrandon.potter@amd.com    dcache = Param.RubyCache("")
4811793Sbrandon.potter@amd.com    max_outstanding_requests = Param.Int(16,
4910146Sandreas.hansson@arm.com        "max requests (incl. prefetches) outstanding")
509356SN/A    deadlock_threshold = Param.Int(500000,
5110146Sandreas.hansson@arm.com        "max outstanding cycles for a request before deadlock/livelock declared")
5210247Sandreas.hansson@arm.com    using_ruby_tester = Param.Bool(False, "")
5310208Sandreas.hansson@arm.com
549352SN/Aclass DMASequencer(RubyPort):
559814SN/A    type = 'DMASequencer'
569243SN/A