Sequencer.py revision 13665:9c7fe3811b88 
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28#          Brad Beckmann
29
30from m5.params import *
31from m5.proxy import *
32from m5.objects.MemObject import MemObject
33
34class RubyPort(MemObject):
35   type = 'RubyPort'
36   abstract = True
37   cxx_header = "mem/ruby/system/RubyPort.hh"
38   version = Param.Int(0, "")
39
40   slave = VectorSlavePort("CPU slave port")
41   master = VectorMasterPort("CPU master port")
42   pio_master_port = MasterPort("Ruby mem master port")
43   mem_master_port = MasterPort("Ruby mem master port")
44   pio_slave_port = SlavePort("Ruby pio slave port")
45   mem_slave_port = SlavePort("Ruby memory port")
46
47   using_ruby_tester = Param.Bool(False, "")
48   no_retry_on_stall = Param.Bool(False, "")
49   ruby_system = Param.RubySystem(Parent.any, "")
50   system = Param.System(Parent.any, "system object")
51   support_data_reqs = Param.Bool(True, "data cache requests supported")
52   support_inst_reqs = Param.Bool(True, "inst cache requests supported")
53   is_cpu_sequencer = Param.Bool(True, "connected to a cpu")
54
55class RubyPortProxy(RubyPort):
56   type = 'RubyPortProxy'
57   cxx_header = "mem/ruby/system/RubyPortProxy.hh"
58
59class RubySequencer(RubyPort):
60   type = 'RubySequencer'
61   cxx_class = 'Sequencer'
62   cxx_header = "mem/ruby/system/Sequencer.hh"
63
64   icache = Param.RubyCache("")
65   dcache = Param.RubyCache("")
66   # Cache latencies currently assessed at the beginning of each access
67   # NOTE: Setting these values to a value greater than one will result in
68   # O3 CPU pipeline bubbles and negatively impact performance
69   # TODO: Latencies should be migrated into each top-level cache controller
70   icache_hit_latency = Param.Cycles(1, "Inst cache hit latency")
71   dcache_hit_latency = Param.Cycles(1, "Data cache hit latency")
72   max_outstanding_requests = Param.Int(16,
73       "max requests (incl. prefetches) outstanding")
74   deadlock_threshold = Param.Cycles(500000,
75       "max outstanding cycles for a request before deadlock/livelock declared")
76   garnet_standalone = Param.Bool(False, "")
77   # id used by protocols that support multiple sequencers per controller
78   # 99 is the dummy default value
79   coreid = Param.Int(99, "CorePair core id")
80
81class DMASequencer(RubyPort):
82   type = 'DMASequencer'
83   cxx_header = "mem/ruby/system/DMASequencer.hh"
84   max_outstanding_requests = Param.Int(64, "max outstanding requests")
85