Sequencer.py revision 11660:cfa97c37117a
12139SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 22139SN/A# All rights reserved. 32139SN/A# 42139SN/A# Redistribution and use in source and binary forms, with or without 52139SN/A# modification, are permitted provided that the following conditions are 62139SN/A# met: redistributions of source code must retain the above copyright 72139SN/A# notice, this list of conditions and the following disclaimer; 82139SN/A# redistributions in binary form must reproduce the above copyright 92139SN/A# notice, this list of conditions and the following disclaimer in the 102139SN/A# documentation and/or other materials provided with the distribution; 112139SN/A# neither the name of the copyright holders nor the names of its 122139SN/A# contributors may be used to endorse or promote products derived from 132139SN/A# this software without specific prior written permission. 142139SN/A# 152139SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162139SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172139SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182139SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192139SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202139SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212139SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222139SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232139SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242139SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252139SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262139SN/A# 272139SN/A# Authors: Steve Reinhardt 282665Ssaidi@eecs.umich.edu# Brad Beckmann 292665Ssaidi@eecs.umich.edu 302139SN/Afrom m5.params import * 314202Sbinkertn@umich.edufrom m5.proxy import * 328961Sgblack@eecs.umich.edufrom MemObject import MemObject 332139SN/A 344202Sbinkertn@umich.educlass RubyPort(MemObject): 352152SN/A type = 'RubyPort' 362152SN/A abstract = True 372139SN/A cxx_header = "mem/ruby/system/RubyPort.hh" 382139SN/A version = Param.Int(0, "") 392139SN/A 402139SN/A slave = VectorSlavePort("CPU slave port") 412139SN/A master = VectorMasterPort("CPU master port") 422152SN/A pio_master_port = MasterPort("Ruby mem master port") 432152SN/A mem_master_port = MasterPort("Ruby mem master port") 442139SN/A pio_slave_port = SlavePort("Ruby pio slave port") 452139SN/A mem_slave_port = SlavePort("Ruby memory port") 462139SN/A 479020Sgblack@eecs.umich.edu using_ruby_tester = Param.Bool(False, "") 484781Snate@binkert.org no_retry_on_stall = Param.Bool(False, "") 497799Sgblack@eecs.umich.edu ruby_system = Param.RubySystem(Parent.any, "") 504781Snate@binkert.org system = Param.System(Parent.any, "system object") 514781Snate@binkert.org support_data_reqs = Param.Bool(True, "data cache requests supported") 523170Sstever@eecs.umich.edu support_inst_reqs = Param.Bool(True, "inst cache requests supported") 535664Sgblack@eecs.umich.edu is_cpu_sequencer = Param.Bool(True, "connected to a cpu") 548105Sgblack@eecs.umich.edu 556179Sksewell@umich.educlass RubyPortProxy(RubyPort): 564781Snate@binkert.org type = 'RubyPortProxy' 574781Snate@binkert.org cxx_header = "mem/ruby/system/RubyPortProxy.hh" 586329Sgblack@eecs.umich.edu 594781Snate@binkert.orgclass RubySequencer(RubyPort): 604781Snate@binkert.org type = 'RubySequencer' 614781Snate@binkert.org cxx_class = 'Sequencer' 624781Snate@binkert.org cxx_header = "mem/ruby/system/Sequencer.hh" 634781Snate@binkert.org 644781Snate@binkert.org icache = Param.RubyCache("") 652139SN/A dcache = Param.RubyCache("") 662139SN/A # Cache latencies currently assessed at the beginning of each access 673546Sgblack@eecs.umich.edu # NOTE: Setting these values to a value greater than one will result in 684202Sbinkertn@umich.edu # O3 CPU pipeline bubbles and negatively impact performance 692152SN/A # TODO: Latencies should be migrated into each top-level cache controller 702152SN/A icache_hit_latency = Param.Cycles(1, "Inst cache hit latency") 712152SN/A dcache_hit_latency = Param.Cycles(1, "Data cache hit latency") 722152SN/A max_outstanding_requests = Param.Int(16, 732152SN/A "max requests (incl. prefetches) outstanding") 742152SN/A deadlock_threshold = Param.Cycles(500000, 752152SN/A "max outstanding cycles for a request before deadlock/livelock declared") 762152SN/A garnet_standalone = Param.Bool(False, "") 772152SN/A # id used by protocols that support multiple sequencers per controller 782152SN/A # 99 is the dummy default value 792152SN/A coreid = Param.Int(99, "CorePair core id") 802152SN/A 812504SN/Aclass DMASequencer(RubyPort): 822504SN/A type = 'DMASequencer' 832504SN/A cxx_header = "mem/ruby/system/DMASequencer.hh" 842504SN/A