Sequencer.py revision 11339:c45bfadcd51b
111723Sar4jc@virginia.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 211723Sar4jc@virginia.edu# All rights reserved. 311723Sar4jc@virginia.edu# 411723Sar4jc@virginia.edu# Redistribution and use in source and binary forms, with or without 511723Sar4jc@virginia.edu# modification, are permitted provided that the following conditions are 611723Sar4jc@virginia.edu# met: redistributions of source code must retain the above copyright 711723Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer; 811723Sar4jc@virginia.edu# redistributions in binary form must reproduce the above copyright 911723Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer in the 1011723Sar4jc@virginia.edu# documentation and/or other materials provided with the distribution; 1111723Sar4jc@virginia.edu# neither the name of the copyright holders nor the names of its 1211723Sar4jc@virginia.edu# contributors may be used to endorse or promote products derived from 1311723Sar4jc@virginia.edu# this software without specific prior written permission. 1411723Sar4jc@virginia.edu# 1511723Sar4jc@virginia.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1611723Sar4jc@virginia.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1711723Sar4jc@virginia.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1811723Sar4jc@virginia.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1911723Sar4jc@virginia.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2011723Sar4jc@virginia.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2111723Sar4jc@virginia.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2211723Sar4jc@virginia.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2311723Sar4jc@virginia.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2411723Sar4jc@virginia.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2511723Sar4jc@virginia.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2611723Sar4jc@virginia.edu# 2711723Sar4jc@virginia.edu# Authors: Steve Reinhardt 2811723Sar4jc@virginia.edu# Brad Beckmann 2911723Sar4jc@virginia.edu 3011723Sar4jc@virginia.edufrom m5.params import * 3111723Sar4jc@virginia.edufrom m5.proxy import * 3211723Sar4jc@virginia.edufrom MemObject import MemObject 3311723Sar4jc@virginia.edu 3411723Sar4jc@virginia.educlass RubyPort(MemObject): 3511723Sar4jc@virginia.edu type = 'RubyPort' 3611723Sar4jc@virginia.edu abstract = True 3711723Sar4jc@virginia.edu cxx_header = "mem/ruby/system/RubyPort.hh" 3811723Sar4jc@virginia.edu version = Param.Int(0, "") 3911723Sar4jc@virginia.edu 4011723Sar4jc@virginia.edu slave = VectorSlavePort("CPU slave port") 4111723Sar4jc@virginia.edu master = VectorMasterPort("CPU master port") 4211723Sar4jc@virginia.edu pio_master_port = MasterPort("Ruby mem master port") 4311723Sar4jc@virginia.edu mem_master_port = MasterPort("Ruby mem master port") 4411723Sar4jc@virginia.edu pio_slave_port = SlavePort("Ruby pio slave port") 4511723Sar4jc@virginia.edu mem_slave_port = SlavePort("Ruby memory port") 4611723Sar4jc@virginia.edu 4711723Sar4jc@virginia.edu using_ruby_tester = Param.Bool(False, "") 4811723Sar4jc@virginia.edu no_retry_on_stall = Param.Bool(False, "") 4911723Sar4jc@virginia.edu ruby_system = Param.RubySystem(Parent.any, "") 5011723Sar4jc@virginia.edu system = Param.System(Parent.any, "system object") 5111723Sar4jc@virginia.edu support_data_reqs = Param.Bool(True, "data cache requests supported") 5211723Sar4jc@virginia.edu support_inst_reqs = Param.Bool(True, "inst cache requests supported") 5311723Sar4jc@virginia.edu is_cpu_sequencer = Param.Bool(True, "connected to a cpu") 5411723Sar4jc@virginia.edu 5511723Sar4jc@virginia.educlass RubyPortProxy(RubyPort): 5611723Sar4jc@virginia.edu type = 'RubyPortProxy' 5711723Sar4jc@virginia.edu cxx_header = "mem/ruby/system/RubyPortProxy.hh" 5811723Sar4jc@virginia.edu 5911723Sar4jc@virginia.educlass RubySequencer(RubyPort): 6011723Sar4jc@virginia.edu type = 'RubySequencer' 6111723Sar4jc@virginia.edu cxx_class = 'Sequencer' 6211723Sar4jc@virginia.edu cxx_header = "mem/ruby/system/Sequencer.hh" 6311723Sar4jc@virginia.edu 6411723Sar4jc@virginia.edu icache = Param.RubyCache("") 6511723Sar4jc@virginia.edu dcache = Param.RubyCache("") 6611723Sar4jc@virginia.edu # Cache latencies currently assessed at the beginning of each access 6711723Sar4jc@virginia.edu # NOTE: Setting these values to a value greater than one will result in 6811723Sar4jc@virginia.edu # O3 CPU pipeline bubbles and negatively impact performance 6911723Sar4jc@virginia.edu # TODO: Latencies should be migrated into each top-level cache controller 7011723Sar4jc@virginia.edu icache_hit_latency = Param.Cycles(1, "Inst cache hit latency") 7111723Sar4jc@virginia.edu dcache_hit_latency = Param.Cycles(1, "Data cache hit latency") 7211723Sar4jc@virginia.edu max_outstanding_requests = Param.Int(16, 7311723Sar4jc@virginia.edu "max requests (incl. prefetches) outstanding") 7411723Sar4jc@virginia.edu deadlock_threshold = Param.Cycles(500000, 7511723Sar4jc@virginia.edu "max outstanding cycles for a request before deadlock/livelock declared") 7611723Sar4jc@virginia.edu using_network_tester = Param.Bool(False, "") 7711723Sar4jc@virginia.edu # id used by protocols that support multiple sequencers per controller 7811723Sar4jc@virginia.edu # 99 is the dummy default value 7911723Sar4jc@virginia.edu coreid = Param.Int(99, "CorePair core id") 8011723Sar4jc@virginia.edu 8111723Sar4jc@virginia.educlass DMASequencer(RubyPort): 8211723Sar4jc@virginia.edu type = 'DMASequencer' 8311723Sar4jc@virginia.edu cxx_header = "mem/ruby/system/DMASequencer.hh" 8411723Sar4jc@virginia.edu