Sequencer.py revision 10525:77787650cbbc
19397Sandreas.hansson@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 29397Sandreas.hansson@arm.com# All rights reserved. 39397Sandreas.hansson@arm.com# 49397Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 59397Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 69397Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 79397Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 89397Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 99397Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 109397Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 119397Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 129397Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 139397Sandreas.hansson@arm.com# this software without specific prior written permission. 149397Sandreas.hansson@arm.com# 159397Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169397Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179397Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189397Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199397Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209397Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219397Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229397Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239397Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249397Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259397Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269397Sandreas.hansson@arm.com# 279397Sandreas.hansson@arm.com# Authors: Steve Reinhardt 289397Sandreas.hansson@arm.com# Brad Beckmann 299397Sandreas.hansson@arm.com 309397Sandreas.hansson@arm.comfrom m5.params import * 319397Sandreas.hansson@arm.comfrom m5.proxy import * 329397Sandreas.hansson@arm.comfrom MemObject import MemObject 339397Sandreas.hansson@arm.com 349397Sandreas.hansson@arm.comclass RubyPort(MemObject): 359397Sandreas.hansson@arm.com type = 'RubyPort' 369397Sandreas.hansson@arm.com abstract = True 379397Sandreas.hansson@arm.com cxx_header = "mem/ruby/system/RubyPort.hh" 389397Sandreas.hansson@arm.com version = Param.Int(0, "") 399397Sandreas.hansson@arm.com 409397Sandreas.hansson@arm.com slave = VectorSlavePort("CPU slave port") 419397Sandreas.hansson@arm.com master = VectorMasterPort("CPU master port") 429397Sandreas.hansson@arm.com pio_master_port = MasterPort("Ruby mem master port") 439397Sandreas.hansson@arm.com mem_master_port = MasterPort("Ruby mem master port") 449397Sandreas.hansson@arm.com pio_slave_port = SlavePort("Ruby pio slave port") 45 mem_slave_port = SlavePort("Ruby memory port") 46 47 using_ruby_tester = Param.Bool(False, "") 48 access_backing_store = Param.Bool(False, 49 "should the rubyport atomically update phys_mem") 50 ruby_system = Param.RubySystem("") 51 system = Param.System(Parent.any, "system object") 52 support_data_reqs = Param.Bool(True, "data cache requests supported") 53 support_inst_reqs = Param.Bool(True, "inst cache requests supported") 54 55class RubyPortProxy(RubyPort): 56 type = 'RubyPortProxy' 57 cxx_header = "mem/ruby/system/RubyPortProxy.hh" 58 59class RubySequencer(RubyPort): 60 type = 'RubySequencer' 61 cxx_class = 'Sequencer' 62 cxx_header = "mem/ruby/system/Sequencer.hh" 63 64 icache = Param.RubyCache("") 65 dcache = Param.RubyCache("") 66 max_outstanding_requests = Param.Int(16, 67 "max requests (incl. prefetches) outstanding") 68 deadlock_threshold = Param.Cycles(500000, 69 "max outstanding cycles for a request before deadlock/livelock declared") 70 using_network_tester = Param.Bool(False, "") 71 72class DMASequencer(MemObject): 73 type = 'DMASequencer' 74 cxx_header = "mem/ruby/system/DMASequencer.hh" 75 76 version = Param.Int(0, "") 77 slave = SlavePort("Device slave port") 78 using_ruby_tester = Param.Bool(False, "") 79 ruby_system = Param.RubySystem(Parent.any, "") 80 system = Param.System(Parent.any, "system object") 81