Sequencer.py revision 8923
17019SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
27019SBrad.Beckmann@amd.com# All rights reserved.
37019SBrad.Beckmann@amd.com#
47019SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without
57019SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are
67019SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright
77019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer;
87019SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright
97019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the
107019SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution;
117019SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its
127019SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from
137019SBrad.Beckmann@amd.com# this software without specific prior written permission.
147019SBrad.Beckmann@amd.com#
157019SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
167019SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
177019SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
187019SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
197019SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
207019SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
217019SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
227019SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
237019SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
247019SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
257019SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
267019SBrad.Beckmann@amd.com#
277019SBrad.Beckmann@amd.com# Authors: Steve Reinhardt
287019SBrad.Beckmann@amd.com#          Brad Beckmann
297019SBrad.Beckmann@amd.com
306876Ssteve.reinhardt@amd.comfrom m5.params import *
316882SBrad.Beckmann@amd.comfrom m5.proxy import *
326876Ssteve.reinhardt@amd.comfrom MemObject import MemObject
336876Ssteve.reinhardt@amd.com
346876Ssteve.reinhardt@amd.comclass RubyPort(MemObject):
356876Ssteve.reinhardt@amd.com    type = 'RubyPort'
366876Ssteve.reinhardt@amd.com    abstract = True
378839Sandreas.hansson@arm.com    slave = VectorSlavePort("CPU slave port")
388839Sandreas.hansson@arm.com    master = VectorMasterPort("CPU master port")
396876Ssteve.reinhardt@amd.com    version = Param.Int(0, "")
408839Sandreas.hansson@arm.com    pio_port = MasterPort("Ruby_pio_port")
417910SBrad.Beckmann@amd.com    using_ruby_tester = Param.Bool(False, "")
428171Stushar@csail.mit.edu    using_network_tester = Param.Bool(False, "")
437915SBrad.Beckmann@amd.com    access_phys_mem = Param.Bool(True,
447915SBrad.Beckmann@amd.com        "should the rubyport atomically update phys_mem")
458436SBrad.Beckmann@amd.com    ruby_system = Param.RubySystem("")
468923Sandreas.hansson@arm.com    system = Param.System(Parent.any, "system object")
478706Sandreas.hansson@arm.com
488706Sandreas.hansson@arm.comclass RubyPortProxy(RubyPort):
498706Sandreas.hansson@arm.com    type = 'RubyPortProxy'
507915SBrad.Beckmann@amd.com
516876Ssteve.reinhardt@amd.comclass RubySequencer(RubyPort):
526876Ssteve.reinhardt@amd.com    type = 'RubySequencer'
536876Ssteve.reinhardt@amd.com    cxx_class = 'Sequencer'
546876Ssteve.reinhardt@amd.com    icache = Param.RubyCache("")
556876Ssteve.reinhardt@amd.com    dcache = Param.RubyCache("")
566876Ssteve.reinhardt@amd.com    max_outstanding_requests = Param.Int(16,
576876Ssteve.reinhardt@amd.com        "max requests (incl. prefetches) outstanding")
586876Ssteve.reinhardt@amd.com    deadlock_threshold = Param.Int(500000,
596876Ssteve.reinhardt@amd.com        "max outstanding cycles for a request before deadlock/livelock declared")
606876Ssteve.reinhardt@amd.com
616876Ssteve.reinhardt@amd.comclass DMASequencer(RubyPort):
626876Ssteve.reinhardt@amd.com    type = 'DMASequencer'
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