Sequencer.py revision 6899
16876Ssteve.reinhardt@amd.comfrom m5.params import *
26882SBrad.Beckmann@amd.comfrom m5.proxy import *
36876Ssteve.reinhardt@amd.comfrom MemObject import MemObject
46876Ssteve.reinhardt@amd.com
56876Ssteve.reinhardt@amd.comclass RubyPort(MemObject):
66876Ssteve.reinhardt@amd.com    type = 'RubyPort'
76876Ssteve.reinhardt@amd.com    abstract = True
86876Ssteve.reinhardt@amd.com    port = VectorPort("M5 port")
96876Ssteve.reinhardt@amd.com    version = Param.Int(0, "")
106882SBrad.Beckmann@amd.com    pio_port = Port("Ruby_pio_port")
116893SBrad.Beckmann@amd.com    physmem = Param.PhysicalMemory("")
126893SBrad.Beckmann@amd.com    physMemPort = Port("port to physical memory")
136876Ssteve.reinhardt@amd.com
146876Ssteve.reinhardt@amd.comclass RubySequencer(RubyPort):
156876Ssteve.reinhardt@amd.com    type = 'RubySequencer'
166876Ssteve.reinhardt@amd.com    cxx_class = 'Sequencer'
176876Ssteve.reinhardt@amd.com    icache = Param.RubyCache("")
186876Ssteve.reinhardt@amd.com    dcache = Param.RubyCache("")
196876Ssteve.reinhardt@amd.com    max_outstanding_requests = Param.Int(16,
206876Ssteve.reinhardt@amd.com        "max requests (incl. prefetches) outstanding")
216876Ssteve.reinhardt@amd.com    deadlock_threshold = Param.Int(500000,
226876Ssteve.reinhardt@amd.com        "max outstanding cycles for a request before deadlock/livelock declared")
236899SBrad.Beckmann@amd.com    using_ruby_tester = Param.Bool(False, "")
246876Ssteve.reinhardt@amd.com
256876Ssteve.reinhardt@amd.comclass DMASequencer(RubyPort):
266876Ssteve.reinhardt@amd.com    type = 'DMASequencer'
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