Sequencer.hh revision 9598:a58b28c17d7f
15222Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 35254Sksewell@umich.edu * All rights reserved. 45254Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 155254Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275254Sksewell@umich.edu */ 285222Sksewell@umich.edu 295254Sksewell@umich.edu#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 305254Sksewell@umich.edu#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 315254Sksewell@umich.edu 325222Sksewell@umich.edu#include <iostream> 335222Sksewell@umich.edu 345222Sksewell@umich.edu#include "base/hashmap.hh" 355222Sksewell@umich.edu#include "mem/protocol/GenericMachineType.hh" 365222Sksewell@umich.edu#include "mem/protocol/RubyRequestType.hh" 375222Sksewell@umich.edu#include "mem/protocol/SequencerRequestType.hh" 385222Sksewell@umich.edu#include "mem/ruby/common/Address.hh" 395222Sksewell@umich.edu#include "mem/ruby/system/CacheMemory.hh" 405222Sksewell@umich.edu#include "mem/ruby/system/RubyPort.hh" 415222Sksewell@umich.edu#include "params/RubySequencer.hh" 425222Sksewell@umich.edu 435222Sksewell@umich.educlass DataBlock; 445222Sksewell@umich.edu 455222Sksewell@umich.edustruct SequencerRequest 465222Sksewell@umich.edu{ 475222Sksewell@umich.edu PacketPtr pkt; 485222Sksewell@umich.edu RubyRequestType m_type; 495222Sksewell@umich.edu Cycles issue_time; 505222Sksewell@umich.edu 515222Sksewell@umich.edu SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, 525222Sksewell@umich.edu Cycles _issue_time) 535222Sksewell@umich.edu : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 545222Sksewell@umich.edu {} 555222Sksewell@umich.edu}; 565222Sksewell@umich.edu 575222Sksewell@umich.edustd::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 585222Sksewell@umich.edu 595222Sksewell@umich.educlass Sequencer : public RubyPort 605222Sksewell@umich.edu{ 615222Sksewell@umich.edu public: 625222Sksewell@umich.edu typedef RubySequencerParams Params; 635222Sksewell@umich.edu Sequencer(const Params *); 645222Sksewell@umich.edu ~Sequencer(); 655222Sksewell@umich.edu 665222Sksewell@umich.edu // Public Methods 675222Sksewell@umich.edu void wakeup(); // Used only for deadlock detection 685222Sksewell@umich.edu 695222Sksewell@umich.edu void printProgress(std::ostream& out) const; 705222Sksewell@umich.edu 715222Sksewell@umich.edu void clearStats(); 725222Sksewell@umich.edu 735222Sksewell@umich.edu void writeCallback(const Address& address, DataBlock& data); 745222Sksewell@umich.edu 755222Sksewell@umich.edu void writeCallback(const Address& address, 765222Sksewell@umich.edu GenericMachineType mach, 775222Sksewell@umich.edu DataBlock& data); 785222Sksewell@umich.edu 795704Snate@binkert.org void writeCallback(const Address& address, 805222Sksewell@umich.edu GenericMachineType mach, 815222Sksewell@umich.edu DataBlock& data, 825222Sksewell@umich.edu Cycles initialRequestTime, 835222Sksewell@umich.edu Cycles forwardRequestTime, 845222Sksewell@umich.edu Cycles firstResponseTime); 855222Sksewell@umich.edu 865222Sksewell@umich.edu void readCallback(const Address& address, DataBlock& data); 875222Sksewell@umich.edu 885222Sksewell@umich.edu void readCallback(const Address& address, 895222Sksewell@umich.edu GenericMachineType mach, 905222Sksewell@umich.edu DataBlock& data); 915222Sksewell@umich.edu 925222Sksewell@umich.edu void readCallback(const Address& address, 935222Sksewell@umich.edu GenericMachineType mach, 945222Sksewell@umich.edu DataBlock& data, 955222Sksewell@umich.edu Cycles initialRequestTime, 965222Sksewell@umich.edu Cycles forwardRequestTime, 975222Sksewell@umich.edu Cycles firstResponseTime); 985222Sksewell@umich.edu 995222Sksewell@umich.edu RequestStatus makeRequest(PacketPtr pkt); 1005222Sksewell@umich.edu bool empty() const; 1015222Sksewell@umich.edu int outstandingCount() const { return m_outstanding_count; } 1025222Sksewell@umich.edu 1035222Sksewell@umich.edu bool isDeadlockEventScheduled() const 1045222Sksewell@umich.edu { return deadlockCheckEvent.scheduled(); } 1055222Sksewell@umich.edu 1065222Sksewell@umich.edu void descheduleDeadlockEvent() 1075222Sksewell@umich.edu { deschedule(deadlockCheckEvent); } 1085222Sksewell@umich.edu 1095222Sksewell@umich.edu void print(std::ostream& out) const; 1105222Sksewell@umich.edu void printStats(std::ostream& out) const; 1115222Sksewell@umich.edu void checkCoherence(const Address& address); 1125222Sksewell@umich.edu 1135222Sksewell@umich.edu void markRemoved(); 1145222Sksewell@umich.edu void removeRequest(SequencerRequest* request); 1155222Sksewell@umich.edu void evictionCallback(const Address& address); 1165222Sksewell@umich.edu void invalidateSC(const Address& address); 1175222Sksewell@umich.edu 1185222Sksewell@umich.edu void recordRequestType(SequencerRequestType requestType); 1195222Sksewell@umich.edu Histogram& getOutstandReqHist() { return m_outstandReqHist; } 1205222Sksewell@umich.edu 1215222Sksewell@umich.edu private: 1225222Sksewell@umich.edu void issueRequest(PacketPtr pkt, RubyRequestType type); 1235222Sksewell@umich.edu 1245222Sksewell@umich.edu void hitCallback(SequencerRequest* request, 1255222Sksewell@umich.edu GenericMachineType mach, 1265222Sksewell@umich.edu DataBlock& data, 1275222Sksewell@umich.edu bool success, 1285222Sksewell@umich.edu Cycles initialRequestTime, 1295222Sksewell@umich.edu Cycles forwardRequestTime, 1305222Sksewell@umich.edu Cycles firstResponseTime); 1315222Sksewell@umich.edu 1325222Sksewell@umich.edu RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); 1335222Sksewell@umich.edu 1345222Sksewell@umich.edu bool handleLlsc(const Address& address, SequencerRequest* request); 1355222Sksewell@umich.edu 1365222Sksewell@umich.edu // Private copy constructor and assignment operator 1375222Sksewell@umich.edu Sequencer(const Sequencer& obj); 1385222Sksewell@umich.edu Sequencer& operator=(const Sequencer& obj); 1395222Sksewell@umich.edu 1405222Sksewell@umich.edu private: 1415222Sksewell@umich.edu int m_max_outstanding_requests; 1425222Sksewell@umich.edu Cycles m_deadlock_threshold; 1435222Sksewell@umich.edu 1445222Sksewell@umich.edu CacheMemory* m_dataCache_ptr; 1455222Sksewell@umich.edu CacheMemory* m_instCache_ptr; 1465222Sksewell@umich.edu 1475222Sksewell@umich.edu typedef m5::hash_map<Address, SequencerRequest*> RequestTable; 1485222Sksewell@umich.edu RequestTable m_writeRequestTable; 1495222Sksewell@umich.edu RequestTable m_readRequestTable; 1505222Sksewell@umich.edu // Global outstanding request count, across all request tables 1515222Sksewell@umich.edu int m_outstanding_count; 1525222Sksewell@umich.edu bool m_deadlock_check_scheduled; 1535222Sksewell@umich.edu 1545222Sksewell@umich.edu uint32_t m_store_waiting_on_load_cycles; 1555222Sksewell@umich.edu uint32_t m_store_waiting_on_store_cycles; 1565222Sksewell@umich.edu uint32_t m_load_waiting_on_store_cycles; 1575222Sksewell@umich.edu uint32_t m_load_waiting_on_load_cycles; 1585222Sksewell@umich.edu 1595222Sksewell@umich.edu bool m_usingNetworkTester; 1605222Sksewell@umich.edu 1615222Sksewell@umich.edu //! Histogram for number of outstanding requests per cycle. 1625222Sksewell@umich.edu Histogram m_outstandReqHist; 1635222Sksewell@umich.edu 1645222Sksewell@umich.edu class SequencerWakeupEvent : public Event 1655222Sksewell@umich.edu { 1665222Sksewell@umich.edu private: 1675222Sksewell@umich.edu Sequencer *m_sequencer_ptr; 1685222Sksewell@umich.edu 1695222Sksewell@umich.edu public: 1705222Sksewell@umich.edu SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {} 1715222Sksewell@umich.edu void process() { m_sequencer_ptr->wakeup(); } 1725222Sksewell@umich.edu const char *description() const { return "Sequencer deadlock check"; } 1735222Sksewell@umich.edu }; 1745222Sksewell@umich.edu 1755222Sksewell@umich.edu SequencerWakeupEvent deadlockCheckEvent; 1765222Sksewell@umich.edu}; 1775222Sksewell@umich.edu 1785222Sksewell@umich.eduinline std::ostream& 1795222Sksewell@umich.eduoperator<<(std::ostream& out, const Sequencer& obj) 1805222Sksewell@umich.edu{ 1815222Sksewell@umich.edu obj.print(out); 1825222Sksewell@umich.edu out << std::flush; 1835222Sksewell@umich.edu return out; 1845222Sksewell@umich.edu} 1855222Sksewell@umich.edu 1865222Sksewell@umich.edu#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 1875222Sksewell@umich.edu