Sequencer.hh revision 7455:586f99bf0dc4 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
31
32#include <iostream>
33
34#include "base/hashmap.hh"
35#include "mem/protocol/AccessModeType.hh"
36#include "mem/protocol/CacheRequestType.hh"
37#include "mem/protocol/GenericMachineType.hh"
38#include "mem/protocol/PrefetchBit.hh"
39#include "mem/ruby/common/Address.hh"
40#include "mem/ruby/common/Consumer.hh"
41#include "mem/ruby/common/Global.hh"
42#include "mem/ruby/system/RubyPort.hh"
43
44class DataBlock;
45class CacheMsg;
46class MachineID;
47class CacheMemory;
48
49class RubySequencerParams;
50
51struct SequencerRequest
52{
53    RubyRequest ruby_request;
54    Time issue_time;
55
56    SequencerRequest(const RubyRequest & _ruby_request, Time _issue_time)
57        : ruby_request(_ruby_request), issue_time(_issue_time)
58    {}
59};
60
61std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
62
63class Sequencer : public RubyPort, public Consumer
64{
65  public:
66    typedef RubySequencerParams Params;
67    Sequencer(const Params *);
68    ~Sequencer();
69
70    // Public Methods
71    void wakeup(); // Used only for deadlock detection
72
73    void printConfig(std::ostream& out) const;
74
75    void printProgress(std::ostream& out) const;
76
77    void writeCallback(const Address& address, DataBlock& data);
78    void readCallback(const Address& address, DataBlock& data);
79
80    RequestStatus makeRequest(const RubyRequest & request);
81    RequestStatus getRequestStatus(const RubyRequest& request);
82    bool empty() const;
83
84    void print(std::ostream& out) const;
85    void printStats(std::ostream& out) const;
86    void checkCoherence(const Address& address);
87
88    void markRemoved();
89    void removeRequest(SequencerRequest* request);
90
91  private:
92    bool tryCacheAccess(const Address& addr, CacheRequestType type,
93                        const Address& pc, AccessModeType access_mode,
94                        int size, DataBlock*& data_ptr);
95    void issueRequest(const RubyRequest& request);
96
97    void hitCallback(SequencerRequest* request, DataBlock& data);
98    bool insertRequest(SequencerRequest* request);
99
100
101    // Private copy constructor and assignment operator
102    Sequencer(const Sequencer& obj);
103    Sequencer& operator=(const Sequencer& obj);
104
105  private:
106    int m_max_outstanding_requests;
107    int m_deadlock_threshold;
108
109    CacheMemory* m_dataCache_ptr;
110    CacheMemory* m_instCache_ptr;
111
112    typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
113    RequestTable m_writeRequestTable;
114    RequestTable m_readRequestTable;
115    // Global outstanding request count, across all request tables
116    int m_outstanding_count;
117    bool m_deadlock_check_scheduled;
118
119    int m_store_waiting_on_load_cycles;
120    int m_store_waiting_on_store_cycles;
121    int m_load_waiting_on_store_cycles;
122    int m_load_waiting_on_load_cycles;
123
124    bool m_usingRubyTester;
125
126    class SequencerWakeupEvent : public Event
127    {
128      private:
129        Sequencer *m_sequencer_ptr;
130
131      public:
132        SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
133        void process() { m_sequencer_ptr->wakeup(); }
134        const char *description() const { return "Sequencer deadlock check"; }
135    };
136
137    SequencerWakeupEvent deadlockCheckEvent;
138};
139
140inline std::ostream&
141operator<<(std::ostream& out, const Sequencer& obj)
142{
143    obj.print(out);
144    out << std::flush;
145    return out;
146}
147
148#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
149
150