Sequencer.hh revision 10301:44839e8febbd
111986Sandreas.sandberg@arm.com/* 211986Sandreas.sandberg@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 311986Sandreas.sandberg@arm.com * All rights reserved. 411986Sandreas.sandberg@arm.com * 511986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711986Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111986Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211986Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311986Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411986Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511986Sandreas.sandberg@arm.com * 1611986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911986Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011986Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111986Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211986Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311986Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411986Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511986Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611986Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711986Sandreas.sandberg@arm.com */ 2811986Sandreas.sandberg@arm.com 2911986Sandreas.sandberg@arm.com#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 3011986Sandreas.sandberg@arm.com#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 3111986Sandreas.sandberg@arm.com 3211986Sandreas.sandberg@arm.com#include <iostream> 3311986Sandreas.sandberg@arm.com 3411986Sandreas.sandberg@arm.com#include "base/hashmap.hh" 3511986Sandreas.sandberg@arm.com#include "mem/protocol/MachineType.hh" 3611986Sandreas.sandberg@arm.com#include "mem/protocol/RubyRequestType.hh" 3711986Sandreas.sandberg@arm.com#include "mem/protocol/SequencerRequestType.hh" 3811986Sandreas.sandberg@arm.com#include "mem/ruby/common/Address.hh" 3911986Sandreas.sandberg@arm.com#include "mem/ruby/structures/CacheMemory.hh" 4011986Sandreas.sandberg@arm.com#include "mem/ruby/system/RubyPort.hh" 4111986Sandreas.sandberg@arm.com#include "params/RubySequencer.hh" 4211986Sandreas.sandberg@arm.com 4311986Sandreas.sandberg@arm.comstruct SequencerRequest 4411986Sandreas.sandberg@arm.com{ 4511986Sandreas.sandberg@arm.com PacketPtr pkt; 4611986Sandreas.sandberg@arm.com RubyRequestType m_type; 4711986Sandreas.sandberg@arm.com Cycles issue_time; 4811986Sandreas.sandberg@arm.com 4911986Sandreas.sandberg@arm.com SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, 5011986Sandreas.sandberg@arm.com Cycles _issue_time) 5111986Sandreas.sandberg@arm.com : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 5211986Sandreas.sandberg@arm.com {} 5311986Sandreas.sandberg@arm.com}; 5411986Sandreas.sandberg@arm.com 5511986Sandreas.sandberg@arm.comstd::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 5611986Sandreas.sandberg@arm.com 5711986Sandreas.sandberg@arm.comclass Sequencer : public RubyPort 5811986Sandreas.sandberg@arm.com{ 5911986Sandreas.sandberg@arm.com public: 6011986Sandreas.sandberg@arm.com typedef RubySequencerParams Params; 6111986Sandreas.sandberg@arm.com Sequencer(const Params *); 6211986Sandreas.sandberg@arm.com ~Sequencer(); 6311986Sandreas.sandberg@arm.com 6411986Sandreas.sandberg@arm.com // Public Methods 6511986Sandreas.sandberg@arm.com void wakeup(); // Used only for deadlock detection 6611986Sandreas.sandberg@arm.com void printProgress(std::ostream& out) const; 6711986Sandreas.sandberg@arm.com void resetStats(); 6811986Sandreas.sandberg@arm.com void collateStats(); 6911986Sandreas.sandberg@arm.com void regStats(); 7011986Sandreas.sandberg@arm.com 7111986Sandreas.sandberg@arm.com void writeCallback(const Address& address, 7211986Sandreas.sandberg@arm.com DataBlock& data, 7311986Sandreas.sandberg@arm.com const bool externalHit = false, 7411986Sandreas.sandberg@arm.com const MachineType mach = MachineType_NUM, 7511986Sandreas.sandberg@arm.com const Cycles initialRequestTime = Cycles(0), 7611986Sandreas.sandberg@arm.com const Cycles forwardRequestTime = Cycles(0), 7711986Sandreas.sandberg@arm.com const Cycles firstResponseTime = Cycles(0)); 7811986Sandreas.sandberg@arm.com 7911986Sandreas.sandberg@arm.com void readCallback(const Address& address, 8011986Sandreas.sandberg@arm.com DataBlock& data, 8111986Sandreas.sandberg@arm.com const bool externalHit = false, 8211986Sandreas.sandberg@arm.com const MachineType mach = MachineType_NUM, 8311986Sandreas.sandberg@arm.com const Cycles initialRequestTime = Cycles(0), 8411986Sandreas.sandberg@arm.com const Cycles forwardRequestTime = Cycles(0), 8511986Sandreas.sandberg@arm.com const Cycles firstResponseTime = Cycles(0)); 8611986Sandreas.sandberg@arm.com 8711986Sandreas.sandberg@arm.com RequestStatus makeRequest(PacketPtr pkt); 8811986Sandreas.sandberg@arm.com bool empty() const; 8911986Sandreas.sandberg@arm.com int outstandingCount() const { return m_outstanding_count; } 9011986Sandreas.sandberg@arm.com 9111986Sandreas.sandberg@arm.com bool isDeadlockEventScheduled() const 9211986Sandreas.sandberg@arm.com { return deadlockCheckEvent.scheduled(); } 9311986Sandreas.sandberg@arm.com 9411986Sandreas.sandberg@arm.com void descheduleDeadlockEvent() 9511986Sandreas.sandberg@arm.com { deschedule(deadlockCheckEvent); } 9611986Sandreas.sandberg@arm.com 9711986Sandreas.sandberg@arm.com void print(std::ostream& out) const; 9811986Sandreas.sandberg@arm.com void checkCoherence(const Address& address); 9911986Sandreas.sandberg@arm.com 10011986Sandreas.sandberg@arm.com void markRemoved(); 10111986Sandreas.sandberg@arm.com void removeRequest(SequencerRequest* request); 10211986Sandreas.sandberg@arm.com void evictionCallback(const Address& address); 10311986Sandreas.sandberg@arm.com void invalidateSC(const Address& address); 10411986Sandreas.sandberg@arm.com 10511986Sandreas.sandberg@arm.com void recordRequestType(SequencerRequestType requestType); 10611986Sandreas.sandberg@arm.com Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } 10712037Sandreas.sandberg@arm.com 10811986Sandreas.sandberg@arm.com Stats::Histogram& getLatencyHist() { return m_latencyHist; } 10911986Sandreas.sandberg@arm.com Stats::Histogram& getTypeLatencyHist(uint32_t t) 11011986Sandreas.sandberg@arm.com { return *m_typeLatencyHist[t]; } 11111986Sandreas.sandberg@arm.com 11211986Sandreas.sandberg@arm.com Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 11311986Sandreas.sandberg@arm.com Stats::Histogram& getHitTypeLatencyHist(uint32_t t) 11411986Sandreas.sandberg@arm.com { return *m_hitTypeLatencyHist[t]; } 11511986Sandreas.sandberg@arm.com 11611986Sandreas.sandberg@arm.com Stats::Histogram& getHitMachLatencyHist(uint32_t t) 11712037Sandreas.sandberg@arm.com { return *m_hitMachLatencyHist[t]; } 11812037Sandreas.sandberg@arm.com 11912037Sandreas.sandberg@arm.com Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 12012037Sandreas.sandberg@arm.com { return *m_hitTypeMachLatencyHist[r][t]; } 121 122 Stats::Histogram& getMissLatencyHist() 123 { return m_missLatencyHist; } 124 Stats::Histogram& getMissTypeLatencyHist(uint32_t t) 125 { return *m_missTypeLatencyHist[t]; } 126 127 Stats::Histogram& getMissMachLatencyHist(uint32_t t) const 128 { return *m_missMachLatencyHist[t]; } 129 130 Stats::Histogram& 131 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const 132 { return *m_missTypeMachLatencyHist[r][t]; } 133 134 Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const 135 { return *m_IssueToInitialDelayHist[t]; } 136 137 Stats::Histogram& 138 getInitialToForwardDelayHist(const MachineType t) const 139 { return *m_InitialToForwardDelayHist[t]; } 140 141 Stats::Histogram& 142 getForwardRequestToFirstResponseHist(const MachineType t) const 143 { return *m_ForwardToFirstResponseDelayHist[t]; } 144 145 Stats::Histogram& 146 getFirstResponseToCompletionDelayHist(const MachineType t) const 147 { return *m_FirstResponseToCompletionDelayHist[t]; } 148 149 Stats::Counter getIncompleteTimes(const MachineType t) const 150 { return m_IncompleteTimes[t]; } 151 152 private: 153 void issueRequest(PacketPtr pkt, RubyRequestType type); 154 155 void hitCallback(SequencerRequest* request, DataBlock& data, 156 bool llscSuccess, 157 const MachineType mach, const bool externalHit, 158 const Cycles initialRequestTime, 159 const Cycles forwardRequestTime, 160 const Cycles firstResponseTime); 161 162 void recordMissLatency(const Cycles t, const RubyRequestType type, 163 const MachineType respondingMach, 164 bool isExternalHit, Cycles issuedTime, 165 Cycles initialRequestTime, 166 Cycles forwardRequestTime, Cycles firstResponseTime, 167 Cycles completionTime); 168 169 RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); 170 bool handleLlsc(const Address& address, SequencerRequest* request); 171 172 // Private copy constructor and assignment operator 173 Sequencer(const Sequencer& obj); 174 Sequencer& operator=(const Sequencer& obj); 175 176 private: 177 int m_max_outstanding_requests; 178 Cycles m_deadlock_threshold; 179 180 CacheMemory* m_dataCache_ptr; 181 CacheMemory* m_instCache_ptr; 182 183 typedef m5::hash_map<Address, SequencerRequest*> RequestTable; 184 RequestTable m_writeRequestTable; 185 RequestTable m_readRequestTable; 186 // Global outstanding request count, across all request tables 187 int m_outstanding_count; 188 bool m_deadlock_check_scheduled; 189 190 //! Counters for recording aliasing information. 191 Stats::Scalar m_store_waiting_on_load; 192 Stats::Scalar m_store_waiting_on_store; 193 Stats::Scalar m_load_waiting_on_store; 194 Stats::Scalar m_load_waiting_on_load; 195 196 bool m_usingNetworkTester; 197 198 //! Histogram for number of outstanding requests per cycle. 199 Stats::Histogram m_outstandReqHist; 200 201 //! Histogram for holding latency profile of all requests. 202 Stats::Histogram m_latencyHist; 203 std::vector<Stats::Histogram *> m_typeLatencyHist; 204 205 //! Histogram for holding latency profile of all requests that 206 //! hit in the controller connected to this sequencer. 207 Stats::Histogram m_hitLatencyHist; 208 std::vector<Stats::Histogram *> m_hitTypeLatencyHist; 209 210 //! Histograms for profiling the latencies for requests that 211 //! did not required external messages. 212 std::vector<Stats::Histogram *> m_hitMachLatencyHist; 213 std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist; 214 215 //! Histogram for holding latency profile of all requests that 216 //! miss in the controller connected to this sequencer. 217 Stats::Histogram m_missLatencyHist; 218 std::vector<Stats::Histogram *> m_missTypeLatencyHist; 219 220 //! Histograms for profiling the latencies for requests that 221 //! required external messages. 222 std::vector<Stats::Histogram *> m_missMachLatencyHist; 223 std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist; 224 225 //! Histograms for recording the breakdown of miss latency 226 std::vector<Stats::Histogram *> m_IssueToInitialDelayHist; 227 std::vector<Stats::Histogram *> m_InitialToForwardDelayHist; 228 std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist; 229 std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist; 230 std::vector<Stats::Counter> m_IncompleteTimes; 231 232 233 class SequencerWakeupEvent : public Event 234 { 235 private: 236 Sequencer *m_sequencer_ptr; 237 238 public: 239 SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {} 240 void process() { m_sequencer_ptr->wakeup(); } 241 const char *description() const { return "Sequencer deadlock check"; } 242 }; 243 244 SequencerWakeupEvent deadlockCheckEvent; 245}; 246 247inline std::ostream& 248operator<<(std::ostream& out, const Sequencer& obj) 249{ 250 obj.print(out); 251 out << std::flush; 252 return out; 253} 254 255#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 256