Sequencer.hh revision 12133
11596Ssaidi@eecs.umich.edu/* 21758Ssaidi@eecs.umich.edu * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 31758Ssaidi@eecs.umich.edu * All rights reserved. 41758Ssaidi@eecs.umich.edu * 51758Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 61758Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 71758Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 81758Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 91758Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 101758Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 111758Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 121758Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 131758Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 141758Ssaidi@eecs.umich.edu * this software without specific prior written permission. 151758Ssaidi@eecs.umich.edu * 161758Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171758Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181758Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191758Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201758Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211758Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221758Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231758Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241758Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251758Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261758Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271758Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 302665Ssaidi@eecs.umich.edu#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 311758Ssaidi@eecs.umich.edu 321772Sbinkertn@umich.edu#include <iostream> 331772Sbinkertn@umich.edu#include <unordered_map> 341596Ssaidi@eecs.umich.edu 351596Ssaidi@eecs.umich.edu#include "mem/protocol/MachineType.hh" 361596Ssaidi@eecs.umich.edu#include "mem/protocol/RubyRequestType.hh" 371596Ssaidi@eecs.umich.edu#include "mem/protocol/SequencerRequestType.hh" 381596Ssaidi@eecs.umich.edu#include "mem/ruby/common/Address.hh" 391596Ssaidi@eecs.umich.edu#include "mem/ruby/structures/CacheMemory.hh" 401596Ssaidi@eecs.umich.edu#include "mem/ruby/system/RubyPort.hh" 411596Ssaidi@eecs.umich.edu#include "params/RubySequencer.hh" 421596Ssaidi@eecs.umich.edu 431596Ssaidi@eecs.umich.edustruct SequencerRequest 441596Ssaidi@eecs.umich.edu{ 451596Ssaidi@eecs.umich.edu PacketPtr pkt; 461596Ssaidi@eecs.umich.edu RubyRequestType m_type; 471596Ssaidi@eecs.umich.edu Cycles issue_time; 481596Ssaidi@eecs.umich.edu 491596Ssaidi@eecs.umich.edu SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, 501596Ssaidi@eecs.umich.edu Cycles _issue_time) 511596Ssaidi@eecs.umich.edu : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 521596Ssaidi@eecs.umich.edu {} 531596Ssaidi@eecs.umich.edu}; 541596Ssaidi@eecs.umich.edu 551596Ssaidi@eecs.umich.edustd::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 561596Ssaidi@eecs.umich.edu 571596Ssaidi@eecs.umich.educlass Sequencer : public RubyPort 581596Ssaidi@eecs.umich.edu{ 591596Ssaidi@eecs.umich.edu public: 601596Ssaidi@eecs.umich.edu typedef RubySequencerParams Params; 611596Ssaidi@eecs.umich.edu Sequencer(const Params *); 621596Ssaidi@eecs.umich.edu ~Sequencer(); 631596Ssaidi@eecs.umich.edu 641596Ssaidi@eecs.umich.edu // Public Methods 651596Ssaidi@eecs.umich.edu void wakeup(); // Used only for deadlock detection 661596Ssaidi@eecs.umich.edu void resetStats(); 671596Ssaidi@eecs.umich.edu void collateStats(); 681596Ssaidi@eecs.umich.edu void regStats(); 691596Ssaidi@eecs.umich.edu 701596Ssaidi@eecs.umich.edu void writeCallback(Addr address, 711596Ssaidi@eecs.umich.edu DataBlock& data, 721596Ssaidi@eecs.umich.edu const bool externalHit = false, 731596Ssaidi@eecs.umich.edu const MachineType mach = MachineType_NUM, 741596Ssaidi@eecs.umich.edu const Cycles initialRequestTime = Cycles(0), 751596Ssaidi@eecs.umich.edu const Cycles forwardRequestTime = Cycles(0), 761596Ssaidi@eecs.umich.edu const Cycles firstResponseTime = Cycles(0)); 771596Ssaidi@eecs.umich.edu 781596Ssaidi@eecs.umich.edu void readCallback(Addr address, 791596Ssaidi@eecs.umich.edu DataBlock& data, 801596Ssaidi@eecs.umich.edu const bool externalHit = false, 811596Ssaidi@eecs.umich.edu const MachineType mach = MachineType_NUM, 821596Ssaidi@eecs.umich.edu const Cycles initialRequestTime = Cycles(0), 831596Ssaidi@eecs.umich.edu const Cycles forwardRequestTime = Cycles(0), 841596Ssaidi@eecs.umich.edu const Cycles firstResponseTime = Cycles(0)); 851596Ssaidi@eecs.umich.edu 861596Ssaidi@eecs.umich.edu RequestStatus makeRequest(PacketPtr pkt); 871596Ssaidi@eecs.umich.edu bool empty() const; 881596Ssaidi@eecs.umich.edu int outstandingCount() const { return m_outstanding_count; } 891596Ssaidi@eecs.umich.edu 901596Ssaidi@eecs.umich.edu bool isDeadlockEventScheduled() const 911596Ssaidi@eecs.umich.edu { return deadlockCheckEvent.scheduled(); } 921596Ssaidi@eecs.umich.edu 931596Ssaidi@eecs.umich.edu void descheduleDeadlockEvent() 941596Ssaidi@eecs.umich.edu { deschedule(deadlockCheckEvent); } 951596Ssaidi@eecs.umich.edu 96 void print(std::ostream& out) const; 97 void checkCoherence(Addr address); 98 99 void markRemoved(); 100 void evictionCallback(Addr address); 101 void invalidateSC(Addr address); 102 int coreId() const { return m_coreId; } 103 104 void recordRequestType(SequencerRequestType requestType); 105 Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } 106 107 Stats::Histogram& getLatencyHist() { return m_latencyHist; } 108 Stats::Histogram& getTypeLatencyHist(uint32_t t) 109 { return *m_typeLatencyHist[t]; } 110 111 Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 112 Stats::Histogram& getHitTypeLatencyHist(uint32_t t) 113 { return *m_hitTypeLatencyHist[t]; } 114 115 Stats::Histogram& getHitMachLatencyHist(uint32_t t) 116 { return *m_hitMachLatencyHist[t]; } 117 118 Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 119 { return *m_hitTypeMachLatencyHist[r][t]; } 120 121 Stats::Histogram& getMissLatencyHist() 122 { return m_missLatencyHist; } 123 Stats::Histogram& getMissTypeLatencyHist(uint32_t t) 124 { return *m_missTypeLatencyHist[t]; } 125 126 Stats::Histogram& getMissMachLatencyHist(uint32_t t) const 127 { return *m_missMachLatencyHist[t]; } 128 129 Stats::Histogram& 130 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const 131 { return *m_missTypeMachLatencyHist[r][t]; } 132 133 Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const 134 { return *m_IssueToInitialDelayHist[t]; } 135 136 Stats::Histogram& 137 getInitialToForwardDelayHist(const MachineType t) const 138 { return *m_InitialToForwardDelayHist[t]; } 139 140 Stats::Histogram& 141 getForwardRequestToFirstResponseHist(const MachineType t) const 142 { return *m_ForwardToFirstResponseDelayHist[t]; } 143 144 Stats::Histogram& 145 getFirstResponseToCompletionDelayHist(const MachineType t) const 146 { return *m_FirstResponseToCompletionDelayHist[t]; } 147 148 Stats::Counter getIncompleteTimes(const MachineType t) const 149 { return m_IncompleteTimes[t]; } 150 151 private: 152 void issueRequest(PacketPtr pkt, RubyRequestType type); 153 154 void hitCallback(SequencerRequest* request, DataBlock& data, 155 bool llscSuccess, 156 const MachineType mach, const bool externalHit, 157 const Cycles initialRequestTime, 158 const Cycles forwardRequestTime, 159 const Cycles firstResponseTime); 160 161 void recordMissLatency(const Cycles t, const RubyRequestType type, 162 const MachineType respondingMach, 163 bool isExternalHit, Cycles issuedTime, 164 Cycles initialRequestTime, 165 Cycles forwardRequestTime, Cycles firstResponseTime, 166 Cycles completionTime); 167 168 RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); 169 bool handleLlsc(Addr address, SequencerRequest* request); 170 171 // Private copy constructor and assignment operator 172 Sequencer(const Sequencer& obj); 173 Sequencer& operator=(const Sequencer& obj); 174 175 private: 176 int m_max_outstanding_requests; 177 Cycles m_deadlock_threshold; 178 179 CacheMemory* m_dataCache_ptr; 180 CacheMemory* m_instCache_ptr; 181 182 // The cache access latency for top-level caches (L0/L1). These are 183 // currently assessed at the beginning of each memory access through the 184 // sequencer. 185 // TODO: Migrate these latencies into top-level cache controllers. 186 Cycles m_data_cache_hit_latency; 187 Cycles m_inst_cache_hit_latency; 188 189 typedef std::unordered_map<Addr, SequencerRequest*> RequestTable; 190 RequestTable m_writeRequestTable; 191 RequestTable m_readRequestTable; 192 // Global outstanding request count, across all request tables 193 int m_outstanding_count; 194 bool m_deadlock_check_scheduled; 195 196 //! Counters for recording aliasing information. 197 Stats::Scalar m_store_waiting_on_load; 198 Stats::Scalar m_store_waiting_on_store; 199 Stats::Scalar m_load_waiting_on_store; 200 Stats::Scalar m_load_waiting_on_load; 201 202 int m_coreId; 203 204 bool m_runningGarnetStandalone; 205 206 //! Histogram for number of outstanding requests per cycle. 207 Stats::Histogram m_outstandReqHist; 208 209 //! Histogram for holding latency profile of all requests. 210 Stats::Histogram m_latencyHist; 211 std::vector<Stats::Histogram *> m_typeLatencyHist; 212 213 //! Histogram for holding latency profile of all requests that 214 //! hit in the controller connected to this sequencer. 215 Stats::Histogram m_hitLatencyHist; 216 std::vector<Stats::Histogram *> m_hitTypeLatencyHist; 217 218 //! Histograms for profiling the latencies for requests that 219 //! did not required external messages. 220 std::vector<Stats::Histogram *> m_hitMachLatencyHist; 221 std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist; 222 223 //! Histogram for holding latency profile of all requests that 224 //! miss in the controller connected to this sequencer. 225 Stats::Histogram m_missLatencyHist; 226 std::vector<Stats::Histogram *> m_missTypeLatencyHist; 227 228 //! Histograms for profiling the latencies for requests that 229 //! required external messages. 230 std::vector<Stats::Histogram *> m_missMachLatencyHist; 231 std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist; 232 233 //! Histograms for recording the breakdown of miss latency 234 std::vector<Stats::Histogram *> m_IssueToInitialDelayHist; 235 std::vector<Stats::Histogram *> m_InitialToForwardDelayHist; 236 std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist; 237 std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist; 238 std::vector<Stats::Counter> m_IncompleteTimes; 239 240 EventFunctionWrapper deadlockCheckEvent; 241}; 242 243inline std::ostream& 244operator<<(std::ostream& out, const Sequencer& obj) 245{ 246 obj.print(out); 247 out << std::flush; 248 return out; 249} 250 251#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 252