Sequencer.hh revision 11025
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org */ 286145Snate@binkert.org 297039Snate@binkert.org#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 307039Snate@binkert.org#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 316145Snate@binkert.org 327055Snate@binkert.org#include <iostream> 337055Snate@binkert.org 347455Snate@binkert.org#include "base/hashmap.hh" 359773Snilay@cs.wisc.edu#include "mem/protocol/MachineType.hh" 368165Snilay@cs.wisc.edu#include "mem/protocol/RubyRequestType.hh" 379104Shestness@cs.utexas.edu#include "mem/protocol/SequencerRequestType.hh" 387039Snate@binkert.org#include "mem/ruby/common/Address.hh" 3910301Snilay@cs.wisc.edu#include "mem/ruby/structures/CacheMemory.hh" 406285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 419171Snilay@cs.wisc.edu#include "params/RubySequencer.hh" 426145Snate@binkert.org 437039Snate@binkert.orgstruct SequencerRequest 447039Snate@binkert.org{ 458615Snilay@cs.wisc.edu PacketPtr pkt; 468615Snilay@cs.wisc.edu RubyRequestType m_type; 479501Snilay@cs.wisc.edu Cycles issue_time; 486285Snate@binkert.org 499501Snilay@cs.wisc.edu SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, 509501Snilay@cs.wisc.edu Cycles _issue_time) 518615Snilay@cs.wisc.edu : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 527039Snate@binkert.org {} 536285Snate@binkert.org}; 546285Snate@binkert.org 556763SBrad.Beckmann@amd.comstd::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 566763SBrad.Beckmann@amd.com 579171Snilay@cs.wisc.educlass Sequencer : public RubyPort 587039Snate@binkert.org{ 597039Snate@binkert.org public: 606876Ssteve.reinhardt@amd.com typedef RubySequencerParams Params; 617039Snate@binkert.org Sequencer(const Params *); 627039Snate@binkert.org ~Sequencer(); 636145Snate@binkert.org 647039Snate@binkert.org // Public Methods 657039Snate@binkert.org void wakeup(); // Used only for deadlock detection 667055Snate@binkert.org void printProgress(std::ostream& out) const; 6710012Snilay@cs.wisc.edu void resetStats(); 6810012Snilay@cs.wisc.edu void collateStats(); 6910012Snilay@cs.wisc.edu void regStats(); 709598Snilay@cs.wisc.edu 7111025Snilay@cs.wisc.edu void writeCallback(Addr address, 727565SBrad.Beckmann@amd.com DataBlock& data, 739773Snilay@cs.wisc.edu const bool externalHit = false, 749773Snilay@cs.wisc.edu const MachineType mach = MachineType_NUM, 759773Snilay@cs.wisc.edu const Cycles initialRequestTime = Cycles(0), 769773Snilay@cs.wisc.edu const Cycles forwardRequestTime = Cycles(0), 779773Snilay@cs.wisc.edu const Cycles firstResponseTime = Cycles(0)); 786145Snate@binkert.org 7911025Snilay@cs.wisc.edu void readCallback(Addr address, 807565SBrad.Beckmann@amd.com DataBlock& data, 819773Snilay@cs.wisc.edu const bool externalHit = false, 829773Snilay@cs.wisc.edu const MachineType mach = MachineType_NUM, 839773Snilay@cs.wisc.edu const Cycles initialRequestTime = Cycles(0), 849773Snilay@cs.wisc.edu const Cycles forwardRequestTime = Cycles(0), 859773Snilay@cs.wisc.edu const Cycles firstResponseTime = Cycles(0)); 867565SBrad.Beckmann@amd.com 878615Snilay@cs.wisc.edu RequestStatus makeRequest(PacketPtr pkt); 887039Snate@binkert.org bool empty() const; 898688Snilay@cs.wisc.edu int outstandingCount() const { return m_outstanding_count; } 908688Snilay@cs.wisc.edu 919598Snilay@cs.wisc.edu bool isDeadlockEventScheduled() const 929598Snilay@cs.wisc.edu { return deadlockCheckEvent.scheduled(); } 939598Snilay@cs.wisc.edu 949598Snilay@cs.wisc.edu void descheduleDeadlockEvent() 959598Snilay@cs.wisc.edu { deschedule(deadlockCheckEvent); } 966145Snate@binkert.org 977055Snate@binkert.org void print(std::ostream& out) const; 9811025Snilay@cs.wisc.edu void checkCoherence(Addr address); 996145Snate@binkert.org 1007455Snate@binkert.org void markRemoved(); 1017039Snate@binkert.org void removeRequest(SequencerRequest* request); 10211025Snilay@cs.wisc.edu void evictionCallback(Addr address); 10311025Snilay@cs.wisc.edu void invalidateSC(Addr address); 1046145Snate@binkert.org 1059104Shestness@cs.utexas.edu void recordRequestType(SequencerRequestType requestType); 10610012Snilay@cs.wisc.edu Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } 1079104Shestness@cs.utexas.edu 10810012Snilay@cs.wisc.edu Stats::Histogram& getLatencyHist() { return m_latencyHist; } 10910012Snilay@cs.wisc.edu Stats::Histogram& getTypeLatencyHist(uint32_t t) 11010012Snilay@cs.wisc.edu { return *m_typeLatencyHist[t]; } 1119773Snilay@cs.wisc.edu 11210012Snilay@cs.wisc.edu Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 11310012Snilay@cs.wisc.edu Stats::Histogram& getHitTypeLatencyHist(uint32_t t) 11410012Snilay@cs.wisc.edu { return *m_hitTypeLatencyHist[t]; } 1159773Snilay@cs.wisc.edu 11610012Snilay@cs.wisc.edu Stats::Histogram& getHitMachLatencyHist(uint32_t t) 11710012Snilay@cs.wisc.edu { return *m_hitMachLatencyHist[t]; } 1189773Snilay@cs.wisc.edu 11910012Snilay@cs.wisc.edu Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 12010012Snilay@cs.wisc.edu { return *m_hitTypeMachLatencyHist[r][t]; } 1219773Snilay@cs.wisc.edu 12210012Snilay@cs.wisc.edu Stats::Histogram& getMissLatencyHist() 12310012Snilay@cs.wisc.edu { return m_missLatencyHist; } 12410012Snilay@cs.wisc.edu Stats::Histogram& getMissTypeLatencyHist(uint32_t t) 12510012Snilay@cs.wisc.edu { return *m_missTypeLatencyHist[t]; } 1269773Snilay@cs.wisc.edu 12710012Snilay@cs.wisc.edu Stats::Histogram& getMissMachLatencyHist(uint32_t t) const 12810012Snilay@cs.wisc.edu { return *m_missMachLatencyHist[t]; } 1299773Snilay@cs.wisc.edu 13010012Snilay@cs.wisc.edu Stats::Histogram& 13110012Snilay@cs.wisc.edu getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const 13210012Snilay@cs.wisc.edu { return *m_missTypeMachLatencyHist[r][t]; } 1339773Snilay@cs.wisc.edu 13410012Snilay@cs.wisc.edu Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const 13510012Snilay@cs.wisc.edu { return *m_IssueToInitialDelayHist[t]; } 1369773Snilay@cs.wisc.edu 13710012Snilay@cs.wisc.edu Stats::Histogram& 13810012Snilay@cs.wisc.edu getInitialToForwardDelayHist(const MachineType t) const 13910012Snilay@cs.wisc.edu { return *m_InitialToForwardDelayHist[t]; } 1409773Snilay@cs.wisc.edu 14110012Snilay@cs.wisc.edu Stats::Histogram& 14210012Snilay@cs.wisc.edu getForwardRequestToFirstResponseHist(const MachineType t) const 14310012Snilay@cs.wisc.edu { return *m_ForwardToFirstResponseDelayHist[t]; } 1449773Snilay@cs.wisc.edu 14510012Snilay@cs.wisc.edu Stats::Histogram& 14610012Snilay@cs.wisc.edu getFirstResponseToCompletionDelayHist(const MachineType t) const 14710012Snilay@cs.wisc.edu { return *m_FirstResponseToCompletionDelayHist[t]; } 1489773Snilay@cs.wisc.edu 14910012Snilay@cs.wisc.edu Stats::Counter getIncompleteTimes(const MachineType t) const 1509773Snilay@cs.wisc.edu { return m_IncompleteTimes[t]; } 1519773Snilay@cs.wisc.edu 1527039Snate@binkert.org private: 1538615Snilay@cs.wisc.edu void issueRequest(PacketPtr pkt, RubyRequestType type); 1546145Snate@binkert.org 1559773Snilay@cs.wisc.edu void hitCallback(SequencerRequest* request, DataBlock& data, 1569773Snilay@cs.wisc.edu bool llscSuccess, 1579773Snilay@cs.wisc.edu const MachineType mach, const bool externalHit, 1589773Snilay@cs.wisc.edu const Cycles initialRequestTime, 1599773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 1609773Snilay@cs.wisc.edu const Cycles firstResponseTime); 1619773Snilay@cs.wisc.edu 1629773Snilay@cs.wisc.edu void recordMissLatency(const Cycles t, const RubyRequestType type, 1639773Snilay@cs.wisc.edu const MachineType respondingMach, 1649773Snilay@cs.wisc.edu bool isExternalHit, Cycles issuedTime, 1659773Snilay@cs.wisc.edu Cycles initialRequestTime, 1669773Snilay@cs.wisc.edu Cycles forwardRequestTime, Cycles firstResponseTime, 1679773Snilay@cs.wisc.edu Cycles completionTime); 1687546SBrad.Beckmann@amd.com 1698615Snilay@cs.wisc.edu RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); 17011025Snilay@cs.wisc.edu bool handleLlsc(Addr address, SequencerRequest* request); 1716145Snate@binkert.org 1727039Snate@binkert.org // Private copy constructor and assignment operator 1737039Snate@binkert.org Sequencer(const Sequencer& obj); 1747039Snate@binkert.org Sequencer& operator=(const Sequencer& obj); 1756145Snate@binkert.org 1767039Snate@binkert.org private: 1777039Snate@binkert.org int m_max_outstanding_requests; 1789184Sandreas.hansson@arm.com Cycles m_deadlock_threshold; 1796145Snate@binkert.org 1807039Snate@binkert.org CacheMemory* m_dataCache_ptr; 1817039Snate@binkert.org CacheMemory* m_instCache_ptr; 1826285Snate@binkert.org 18311019Sjthestness@gmail.com // The cache access latency for top-level caches (L0/L1). These are 18411019Sjthestness@gmail.com // currently assessed at the beginning of each memory access through the 18511019Sjthestness@gmail.com // sequencer. 18611019Sjthestness@gmail.com // TODO: Migrate these latencies into top-level cache controllers. 18711019Sjthestness@gmail.com Cycles m_data_cache_hit_latency; 18811019Sjthestness@gmail.com Cycles m_inst_cache_hit_latency; 18911019Sjthestness@gmail.com 19011025Snilay@cs.wisc.edu typedef m5::hash_map<Addr, SequencerRequest*> RequestTable; 1917455Snate@binkert.org RequestTable m_writeRequestTable; 1927455Snate@binkert.org RequestTable m_readRequestTable; 1937039Snate@binkert.org // Global outstanding request count, across all request tables 1947039Snate@binkert.org int m_outstanding_count; 1957039Snate@binkert.org bool m_deadlock_check_scheduled; 1966145Snate@binkert.org 19710012Snilay@cs.wisc.edu //! Counters for recording aliasing information. 19810012Snilay@cs.wisc.edu Stats::Scalar m_store_waiting_on_load; 19910012Snilay@cs.wisc.edu Stats::Scalar m_store_waiting_on_store; 20010012Snilay@cs.wisc.edu Stats::Scalar m_load_waiting_on_store; 20110012Snilay@cs.wisc.edu Stats::Scalar m_load_waiting_on_load; 2026859Sdrh5@cs.wisc.edu 2038171Stushar@csail.mit.edu bool m_usingNetworkTester; 2048171Stushar@csail.mit.edu 2059598Snilay@cs.wisc.edu //! Histogram for number of outstanding requests per cycle. 20610012Snilay@cs.wisc.edu Stats::Histogram m_outstandReqHist; 2079598Snilay@cs.wisc.edu 2089773Snilay@cs.wisc.edu //! Histogram for holding latency profile of all requests. 20910012Snilay@cs.wisc.edu Stats::Histogram m_latencyHist; 21010012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_typeLatencyHist; 2119773Snilay@cs.wisc.edu 2129773Snilay@cs.wisc.edu //! Histogram for holding latency profile of all requests that 2139773Snilay@cs.wisc.edu //! hit in the controller connected to this sequencer. 21410012Snilay@cs.wisc.edu Stats::Histogram m_hitLatencyHist; 21510012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_hitTypeLatencyHist; 2169773Snilay@cs.wisc.edu 2179773Snilay@cs.wisc.edu //! Histograms for profiling the latencies for requests that 2189773Snilay@cs.wisc.edu //! did not required external messages. 21910012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_hitMachLatencyHist; 22010012Snilay@cs.wisc.edu std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist; 2219773Snilay@cs.wisc.edu 2229773Snilay@cs.wisc.edu //! Histogram for holding latency profile of all requests that 2239773Snilay@cs.wisc.edu //! miss in the controller connected to this sequencer. 22410012Snilay@cs.wisc.edu Stats::Histogram m_missLatencyHist; 22510012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_missTypeLatencyHist; 2269773Snilay@cs.wisc.edu 2279773Snilay@cs.wisc.edu //! Histograms for profiling the latencies for requests that 2289773Snilay@cs.wisc.edu //! required external messages. 22910012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_missMachLatencyHist; 23010012Snilay@cs.wisc.edu std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist; 2319773Snilay@cs.wisc.edu 2329773Snilay@cs.wisc.edu //! Histograms for recording the breakdown of miss latency 23310012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_IssueToInitialDelayHist; 23410012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_InitialToForwardDelayHist; 23510012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist; 23610012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist; 23710012Snilay@cs.wisc.edu std::vector<Stats::Counter> m_IncompleteTimes; 2389773Snilay@cs.wisc.edu 2399773Snilay@cs.wisc.edu 2407039Snate@binkert.org class SequencerWakeupEvent : public Event 2417039Snate@binkert.org { 2427039Snate@binkert.org private: 2437039Snate@binkert.org Sequencer *m_sequencer_ptr; 2446899SBrad.Beckmann@amd.com 2457039Snate@binkert.org public: 2467039Snate@binkert.org SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {} 2477039Snate@binkert.org void process() { m_sequencer_ptr->wakeup(); } 2487039Snate@binkert.org const char *description() const { return "Sequencer deadlock check"; } 2497039Snate@binkert.org }; 2506886SBrad.Beckmann@amd.com 2517039Snate@binkert.org SequencerWakeupEvent deadlockCheckEvent; 2526145Snate@binkert.org}; 2536145Snate@binkert.org 2547055Snate@binkert.orginline std::ostream& 2557055Snate@binkert.orgoperator<<(std::ostream& out, const Sequencer& obj) 2566145Snate@binkert.org{ 2577039Snate@binkert.org obj.print(out); 2587055Snate@binkert.org out << std::flush; 2597039Snate@binkert.org return out; 2606145Snate@binkert.org} 2616145Snate@binkert.org 2627039Snate@binkert.org#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 263