Sequencer.cc revision 9171 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/misc.hh"
30#include "base/str.hh"
31#include "config/the_isa.hh"
32#if THE_ISA == X86_ISA
33#include "arch/x86/insts/microldstop.hh"
34#endif // X86_ISA
35#include "cpu/testers/rubytest/RubyTester.hh"
36#include "debug/MemoryAccess.hh"
37#include "debug/ProtocolTrace.hh"
38#include "debug/RubySequencer.hh"
39#include "debug/RubyStats.hh"
40#include "mem/protocol/PrefetchBit.hh"
41#include "mem/protocol/RubyAccessMode.hh"
42#include "mem/ruby/buffers/MessageBuffer.hh"
43#include "mem/ruby/common/Global.hh"
44#include "mem/ruby/profiler/Profiler.hh"
45#include "mem/ruby/slicc_interface/RubyRequest.hh"
46#include "mem/ruby/system/Sequencer.hh"
47#include "mem/ruby/system/System.hh"
48#include "mem/packet.hh"
49
50using namespace std;
51
52Sequencer *
53RubySequencerParams::create()
54{
55    return new Sequencer(this);
56}
57
58Sequencer::Sequencer(const Params *p)
59    : RubyPort(p), deadlockCheckEvent(this)
60{
61    m_store_waiting_on_load_cycles = 0;
62    m_store_waiting_on_store_cycles = 0;
63    m_load_waiting_on_store_cycles = 0;
64    m_load_waiting_on_load_cycles = 0;
65
66    m_outstanding_count = 0;
67
68    m_instCache_ptr = p->icache;
69    m_dataCache_ptr = p->dcache;
70    m_max_outstanding_requests = p->max_outstanding_requests;
71    m_deadlock_threshold = p->deadlock_threshold;
72
73    assert(m_max_outstanding_requests > 0);
74    assert(m_deadlock_threshold > 0);
75    assert(m_instCache_ptr != NULL);
76    assert(m_dataCache_ptr != NULL);
77
78    m_usingNetworkTester = p->using_network_tester;
79}
80
81Sequencer::~Sequencer()
82{
83}
84
85void
86Sequencer::wakeup()
87{
88    // Check for deadlock of any of the requests
89    Time current_time = g_system_ptr->getTime();
90
91    // Check across all outstanding requests
92    int total_outstanding = 0;
93
94    RequestTable::iterator read = m_readRequestTable.begin();
95    RequestTable::iterator read_end = m_readRequestTable.end();
96    for (; read != read_end; ++read) {
97        SequencerRequest* request = read->second;
98        if (current_time - request->issue_time < m_deadlock_threshold)
99            continue;
100
101        panic("Possible Deadlock detected. Aborting!\n"
102             "version: %d request.paddr: 0x%x m_readRequestTable: %d "
103             "current time: %u issue_time: %d difference: %d\n", m_version,
104             Address(request->pkt->getAddr()), m_readRequestTable.size(),
105             current_time, request->issue_time,
106             current_time - request->issue_time);
107    }
108
109    RequestTable::iterator write = m_writeRequestTable.begin();
110    RequestTable::iterator write_end = m_writeRequestTable.end();
111    for (; write != write_end; ++write) {
112        SequencerRequest* request = write->second;
113        if (current_time - request->issue_time < m_deadlock_threshold)
114            continue;
115
116        panic("Possible Deadlock detected. Aborting!\n"
117             "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
118             "current time: %u issue_time: %d difference: %d\n", m_version,
119             Address(request->pkt->getAddr()), m_writeRequestTable.size(),
120             current_time, request->issue_time,
121             current_time - request->issue_time);
122    }
123
124    total_outstanding += m_writeRequestTable.size();
125    total_outstanding += m_readRequestTable.size();
126
127    assert(m_outstanding_count == total_outstanding);
128
129    if (m_outstanding_count > 0) {
130        // If there are still outstanding requests, keep checking
131        schedule(deadlockCheckEvent,
132                 m_deadlock_threshold * g_system_ptr->getClock() +
133                 curTick());
134    }
135}
136
137void
138Sequencer::printStats(ostream & out) const
139{
140    out << "Sequencer: " << m_name << endl
141        << "  store_waiting_on_load_cycles: "
142        << m_store_waiting_on_load_cycles << endl
143        << "  store_waiting_on_store_cycles: "
144        << m_store_waiting_on_store_cycles << endl
145        << "  load_waiting_on_load_cycles: "
146        << m_load_waiting_on_load_cycles << endl
147        << "  load_waiting_on_store_cycles: "
148        << m_load_waiting_on_store_cycles << endl;
149}
150
151void
152Sequencer::printProgress(ostream& out) const
153{
154#if 0
155    int total_demand = 0;
156    out << "Sequencer Stats Version " << m_version << endl;
157    out << "Current time = " << g_system_ptr->getTime() << endl;
158    out << "---------------" << endl;
159    out << "outstanding requests" << endl;
160
161    out << "proc " << m_Read
162        << " version Requests = " << m_readRequestTable.size() << endl;
163
164    // print the request table
165    RequestTable::iterator read = m_readRequestTable.begin();
166    RequestTable::iterator read_end = m_readRequestTable.end();
167    for (; read != read_end; ++read) {
168        SequencerRequest* request = read->second;
169        out << "\tRequest[ " << i << " ] = " << request->type
170            << " Address " << rkeys[i]
171            << " Posted " << request->issue_time
172            << " PF " << PrefetchBit_No << endl;
173        total_demand++;
174    }
175
176    out << "proc " << m_version
177        << " Write Requests = " << m_writeRequestTable.size << endl;
178
179    // print the request table
180    RequestTable::iterator write = m_writeRequestTable.begin();
181    RequestTable::iterator write_end = m_writeRequestTable.end();
182    for (; write != write_end; ++write) {
183        SequencerRequest* request = write->second;
184        out << "\tRequest[ " << i << " ] = " << request.getType()
185            << " Address " << wkeys[i]
186            << " Posted " << request.getTime()
187            << " PF " << request.getPrefetch() << endl;
188        if (request.getPrefetch() == PrefetchBit_No) {
189            total_demand++;
190        }
191    }
192
193    out << endl;
194
195    out << "Total Number Outstanding: " << m_outstanding_count << endl
196        << "Total Number Demand     : " << total_demand << endl
197        << "Total Number Prefetches : " << m_outstanding_count - total_demand
198        << endl << endl << endl;
199#endif
200}
201
202// Insert the request on the correct request table.  Return true if
203// the entry was already present.
204RequestStatus
205Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
206{
207    assert(m_outstanding_count ==
208        (m_writeRequestTable.size() + m_readRequestTable.size()));
209
210    // See if we should schedule a deadlock check
211    if (deadlockCheckEvent.scheduled() == false) {
212        schedule(deadlockCheckEvent,
213                 m_deadlock_threshold * g_system_ptr->getClock()
214                 + curTick());
215    }
216
217    Address line_addr(pkt->getAddr());
218    line_addr.makeLineAddress();
219    if ((request_type == RubyRequestType_ST) ||
220        (request_type == RubyRequestType_RMW_Read) ||
221        (request_type == RubyRequestType_RMW_Write) ||
222        (request_type == RubyRequestType_Load_Linked) ||
223        (request_type == RubyRequestType_Store_Conditional) ||
224        (request_type == RubyRequestType_Locked_RMW_Read) ||
225        (request_type == RubyRequestType_Locked_RMW_Write) ||
226        (request_type == RubyRequestType_FLUSH)) {
227
228        // Check if there is any outstanding read request for the same
229        // cache line.
230        if (m_readRequestTable.count(line_addr) > 0) {
231            m_store_waiting_on_load_cycles++;
232            return RequestStatus_Aliased;
233        }
234
235        pair<RequestTable::iterator, bool> r =
236            m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
237        if (r.second) {
238            RequestTable::iterator i = r.first;
239            i->second = new SequencerRequest(pkt, request_type,
240                                             g_system_ptr->getTime());
241            m_outstanding_count++;
242        } else {
243          // There is an outstanding write request for the cache line
244          m_store_waiting_on_store_cycles++;
245          return RequestStatus_Aliased;
246        }
247    } else {
248        // Check if there is any outstanding write request for the same
249        // cache line.
250        if (m_writeRequestTable.count(line_addr) > 0) {
251            m_load_waiting_on_store_cycles++;
252            return RequestStatus_Aliased;
253        }
254
255        pair<RequestTable::iterator, bool> r =
256            m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
257
258        if (r.second) {
259            RequestTable::iterator i = r.first;
260            i->second = new SequencerRequest(pkt, request_type,
261                                             g_system_ptr->getTime());
262            m_outstanding_count++;
263        } else {
264            // There is an outstanding read request for the cache line
265            m_load_waiting_on_load_cycles++;
266            return RequestStatus_Aliased;
267        }
268    }
269
270    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
271    assert(m_outstanding_count ==
272        (m_writeRequestTable.size() + m_readRequestTable.size()));
273
274    return RequestStatus_Ready;
275}
276
277void
278Sequencer::markRemoved()
279{
280    m_outstanding_count--;
281    assert(m_outstanding_count ==
282           m_writeRequestTable.size() + m_readRequestTable.size());
283}
284
285void
286Sequencer::removeRequest(SequencerRequest* srequest)
287{
288    assert(m_outstanding_count ==
289           m_writeRequestTable.size() + m_readRequestTable.size());
290
291    Address line_addr(srequest->pkt->getAddr());
292    line_addr.makeLineAddress();
293    if ((srequest->m_type == RubyRequestType_ST) ||
294        (srequest->m_type == RubyRequestType_RMW_Read) ||
295        (srequest->m_type == RubyRequestType_RMW_Write) ||
296        (srequest->m_type == RubyRequestType_Load_Linked) ||
297        (srequest->m_type == RubyRequestType_Store_Conditional) ||
298        (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
299        (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
300        m_writeRequestTable.erase(line_addr);
301    } else {
302        m_readRequestTable.erase(line_addr);
303    }
304
305    markRemoved();
306}
307
308bool
309Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
310{
311    //
312    // The success flag indicates whether the LLSC operation was successful.
313    // LL ops will always succeed, but SC may fail if the cache line is no
314    // longer locked.
315    //
316    bool success = true;
317    if (request->m_type == RubyRequestType_Store_Conditional) {
318        if (!m_dataCache_ptr->isLocked(address, m_version)) {
319            //
320            // For failed SC requests, indicate the failure to the cpu by
321            // setting the extra data to zero.
322            //
323            request->pkt->req->setExtraData(0);
324            success = false;
325        } else {
326            //
327            // For successful SC requests, indicate the success to the cpu by
328            // setting the extra data to one.
329            //
330            request->pkt->req->setExtraData(1);
331        }
332        //
333        // Independent of success, all SC operations must clear the lock
334        //
335        m_dataCache_ptr->clearLocked(address);
336    } else if (request->m_type == RubyRequestType_Load_Linked) {
337        //
338        // Note: To fully follow Alpha LLSC semantics, should the LL clear any
339        // previously locked cache lines?
340        //
341        m_dataCache_ptr->setLocked(address, m_version);
342    } else if ((m_dataCache_ptr->isTagPresent(address)) &&
343               (m_dataCache_ptr->isLocked(address, m_version))) {
344        //
345        // Normal writes should clear the locked address
346        //
347        m_dataCache_ptr->clearLocked(address);
348    }
349    return success;
350}
351
352void
353Sequencer::writeCallback(const Address& address, DataBlock& data)
354{
355    writeCallback(address, GenericMachineType_NULL, data);
356}
357
358void
359Sequencer::writeCallback(const Address& address,
360                         GenericMachineType mach,
361                         DataBlock& data)
362{
363    writeCallback(address, mach, data, 0, 0, 0);
364}
365
366void
367Sequencer::writeCallback(const Address& address,
368                         GenericMachineType mach,
369                         DataBlock& data,
370                         Time initialRequestTime,
371                         Time forwardRequestTime,
372                         Time firstResponseTime)
373{
374    assert(address == line_address(address));
375    assert(m_writeRequestTable.count(line_address(address)));
376
377    RequestTable::iterator i = m_writeRequestTable.find(address);
378    assert(i != m_writeRequestTable.end());
379    SequencerRequest* request = i->second;
380
381    m_writeRequestTable.erase(i);
382    markRemoved();
383
384    assert((request->m_type == RubyRequestType_ST) ||
385           (request->m_type == RubyRequestType_ATOMIC) ||
386           (request->m_type == RubyRequestType_RMW_Read) ||
387           (request->m_type == RubyRequestType_RMW_Write) ||
388           (request->m_type == RubyRequestType_Load_Linked) ||
389           (request->m_type == RubyRequestType_Store_Conditional) ||
390           (request->m_type == RubyRequestType_Locked_RMW_Read) ||
391           (request->m_type == RubyRequestType_Locked_RMW_Write) ||
392           (request->m_type == RubyRequestType_FLUSH));
393
394
395    //
396    // For Alpha, properly handle LL, SC, and write requests with respect to
397    // locked cache blocks.
398    //
399    // Not valid for Network_test protocl
400    //
401    bool success = true;
402    if(!m_usingNetworkTester)
403        success = handleLlsc(address, request);
404
405    if (request->m_type == RubyRequestType_Locked_RMW_Read) {
406        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
407    } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
408        m_controller->unblock(address);
409    }
410
411    hitCallback(request, mach, data, success,
412                initialRequestTime, forwardRequestTime, firstResponseTime);
413}
414
415void
416Sequencer::readCallback(const Address& address, DataBlock& data)
417{
418    readCallback(address, GenericMachineType_NULL, data);
419}
420
421void
422Sequencer::readCallback(const Address& address,
423                        GenericMachineType mach,
424                        DataBlock& data)
425{
426    readCallback(address, mach, data, 0, 0, 0);
427}
428
429void
430Sequencer::readCallback(const Address& address,
431                        GenericMachineType mach,
432                        DataBlock& data,
433                        Time initialRequestTime,
434                        Time forwardRequestTime,
435                        Time firstResponseTime)
436{
437    assert(address == line_address(address));
438    assert(m_readRequestTable.count(line_address(address)));
439
440    RequestTable::iterator i = m_readRequestTable.find(address);
441    assert(i != m_readRequestTable.end());
442    SequencerRequest* request = i->second;
443
444    m_readRequestTable.erase(i);
445    markRemoved();
446
447    assert((request->m_type == RubyRequestType_LD) ||
448           (request->m_type == RubyRequestType_IFETCH));
449
450    hitCallback(request, mach, data, true,
451                initialRequestTime, forwardRequestTime, firstResponseTime);
452}
453
454void
455Sequencer::hitCallback(SequencerRequest* srequest,
456                       GenericMachineType mach,
457                       DataBlock& data,
458                       bool success,
459                       Time initialRequestTime,
460                       Time forwardRequestTime,
461                       Time firstResponseTime)
462{
463    PacketPtr pkt = srequest->pkt;
464    Address request_address(pkt->getAddr());
465    Address request_line_address(pkt->getAddr());
466    request_line_address.makeLineAddress();
467    RubyRequestType type = srequest->m_type;
468    Time issued_time = srequest->issue_time;
469
470    // Set this cache entry to the most recently used
471    if (type == RubyRequestType_IFETCH) {
472        m_instCache_ptr->setMRU(request_line_address);
473    } else {
474        m_dataCache_ptr->setMRU(request_line_address);
475    }
476
477    assert(g_system_ptr->getTime() >= issued_time);
478    Time miss_latency = g_system_ptr->getTime() - issued_time;
479
480    // Profile the miss latency for all non-zero demand misses
481    if (miss_latency != 0) {
482        g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
483
484        if (mach == GenericMachineType_L1Cache_wCC) {
485            g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
486                                                   initialRequestTime,
487                                                   forwardRequestTime,
488                                                   firstResponseTime,
489                                                   g_system_ptr->getTime());
490        }
491
492        if (mach == GenericMachineType_Directory) {
493            g_system_ptr->getProfiler()->missLatencyDir(issued_time,
494                                                   initialRequestTime,
495                                                   forwardRequestTime,
496                                                   firstResponseTime,
497                                                   g_system_ptr->getTime());
498        }
499
500        DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
501                 curTick(), m_version, "Seq",
502                 success ? "Done" : "SC_Failed", "", "",
503                 request_address, miss_latency);
504    }
505
506    // update the data
507    if (g_system_ptr->m_warmup_enabled) {
508        assert(pkt->getPtr<uint8_t>(false) != NULL);
509        data.setData(pkt->getPtr<uint8_t>(false),
510                     request_address.getOffset(), pkt->getSize());
511    } else if (pkt->getPtr<uint8_t>(true) != NULL) {
512        if ((type == RubyRequestType_LD) ||
513            (type == RubyRequestType_IFETCH) ||
514            (type == RubyRequestType_RMW_Read) ||
515            (type == RubyRequestType_Locked_RMW_Read) ||
516            (type == RubyRequestType_Load_Linked)) {
517            memcpy(pkt->getPtr<uint8_t>(true),
518                   data.getData(request_address.getOffset(), pkt->getSize()),
519                   pkt->getSize());
520        } else {
521            data.setData(pkt->getPtr<uint8_t>(true),
522                         request_address.getOffset(), pkt->getSize());
523        }
524    } else {
525        DPRINTF(MemoryAccess,
526                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
527                RubyRequestType_to_string(type));
528    }
529
530    // If using the RubyTester, update the RubyTester sender state's
531    // subBlock with the recieved data.  The tester will later access
532    // this state.
533    // Note: RubyPort will access it's sender state before the
534    // RubyTester.
535    if (m_usingRubyTester) {
536        RubyPort::SenderState *requestSenderState =
537            safe_cast<RubyPort::SenderState*>(pkt->senderState);
538        RubyTester::SenderState* testerSenderState =
539            safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
540        testerSenderState->subBlock->mergeFrom(data);
541    }
542
543    delete srequest;
544
545    if (g_system_ptr->m_warmup_enabled) {
546        delete pkt;
547        g_system_ptr->m_cache_recorder->enqueueNextFetchRequest();
548    } else if (g_system_ptr->m_cooldown_enabled) {
549        delete pkt;
550        g_system_ptr->m_cache_recorder->enqueueNextFlushRequest();
551    } else {
552        ruby_hit_callback(pkt);
553    }
554}
555
556bool
557Sequencer::empty() const
558{
559    return m_writeRequestTable.empty() && m_readRequestTable.empty();
560}
561
562RequestStatus
563Sequencer::makeRequest(PacketPtr pkt)
564{
565    if (m_outstanding_count >= m_max_outstanding_requests) {
566        return RequestStatus_BufferFull;
567    }
568
569    RubyRequestType primary_type = RubyRequestType_NULL;
570    RubyRequestType secondary_type = RubyRequestType_NULL;
571
572    if (pkt->isLLSC()) {
573        //
574        // Alpha LL/SC instructions need to be handled carefully by the cache
575        // coherence protocol to ensure they follow the proper semantics. In
576        // particular, by identifying the operations as atomic, the protocol
577        // should understand that migratory sharing optimizations should not
578        // be performed (i.e. a load between the LL and SC should not steal
579        // away exclusive permission).
580        //
581        if (pkt->isWrite()) {
582            DPRINTF(RubySequencer, "Issuing SC\n");
583            primary_type = RubyRequestType_Store_Conditional;
584        } else {
585            DPRINTF(RubySequencer, "Issuing LL\n");
586            assert(pkt->isRead());
587            primary_type = RubyRequestType_Load_Linked;
588        }
589        secondary_type = RubyRequestType_ATOMIC;
590    } else if (pkt->req->isLocked()) {
591        //
592        // x86 locked instructions are translated to store cache coherence
593        // requests because these requests should always be treated as read
594        // exclusive operations and should leverage any migratory sharing
595        // optimization built into the protocol.
596        //
597        if (pkt->isWrite()) {
598            DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
599            primary_type = RubyRequestType_Locked_RMW_Write;
600        } else {
601            DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
602            assert(pkt->isRead());
603            primary_type = RubyRequestType_Locked_RMW_Read;
604        }
605        secondary_type = RubyRequestType_ST;
606    } else {
607        if (pkt->isRead()) {
608            if (pkt->req->isInstFetch()) {
609                primary_type = secondary_type = RubyRequestType_IFETCH;
610            } else {
611#if THE_ISA == X86_ISA
612                uint32_t flags = pkt->req->getFlags();
613                bool storeCheck = flags &
614                        (TheISA::StoreCheck << TheISA::FlagShift);
615#else
616                bool storeCheck = false;
617#endif // X86_ISA
618                if (storeCheck) {
619                    primary_type = RubyRequestType_RMW_Read;
620                    secondary_type = RubyRequestType_ST;
621                } else {
622                    primary_type = secondary_type = RubyRequestType_LD;
623                }
624            }
625        } else if (pkt->isWrite()) {
626            //
627            // Note: M5 packets do not differentiate ST from RMW_Write
628            //
629            primary_type = secondary_type = RubyRequestType_ST;
630        } else if (pkt->isFlush()) {
631          primary_type = secondary_type = RubyRequestType_FLUSH;
632        } else {
633            panic("Unsupported ruby packet type\n");
634        }
635    }
636
637    RequestStatus status = insertRequest(pkt, primary_type);
638    if (status != RequestStatus_Ready)
639        return status;
640
641    issueRequest(pkt, secondary_type);
642
643    // TODO: issue hardware prefetches here
644    return RequestStatus_Issued;
645}
646
647void
648Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
649{
650    int proc_id = -1;
651    if (pkt != NULL && pkt->req->hasContextId()) {
652        proc_id = pkt->req->contextId();
653    }
654
655    // If valid, copy the pc to the ruby request
656    Addr pc = 0;
657    if (pkt->req->hasPC()) {
658        pc = pkt->req->getPC();
659    }
660
661    RubyRequest *msg = new RubyRequest(pkt->getAddr(),
662                                       pkt->getPtr<uint8_t>(true),
663                                       pkt->getSize(), pc, secondary_type,
664                                       RubyAccessMode_Supervisor, pkt,
665                                       PrefetchBit_No, proc_id);
666
667    DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
668            curTick(), m_version, "Seq", "Begin", "", "",
669            msg->getPhysicalAddress(),
670            RubyRequestType_to_string(secondary_type));
671
672    Time latency = 0;  // initialzed to an null value
673
674    if (secondary_type == RubyRequestType_IFETCH)
675        latency = m_instCache_ptr->getLatency();
676    else
677        latency = m_dataCache_ptr->getLatency();
678
679    // Send the message to the cache controller
680    assert(latency > 0);
681
682    assert(m_mandatory_q_ptr != NULL);
683    m_mandatory_q_ptr->enqueue(msg, latency);
684}
685
686template <class KEY, class VALUE>
687std::ostream &
688operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
689{
690    typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
691    typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
692
693    out << "[";
694    for (; i != end; ++i)
695        out << " " << i->first << "=" << i->second;
696    out << " ]";
697
698    return out;
699}
700
701void
702Sequencer::print(ostream& out) const
703{
704    out << "[Sequencer: " << m_version
705        << ", outstanding requests: " << m_outstanding_count
706        << ", read request table: " << m_readRequestTable
707        << ", write request table: " << m_writeRequestTable
708        << "]";
709}
710
711// this can be called from setState whenever coherence permissions are
712// upgraded when invoked, coherence violations will be checked for the
713// given block
714void
715Sequencer::checkCoherence(const Address& addr)
716{
717#ifdef CHECK_COHERENCE
718    g_system_ptr->checkGlobalCoherenceInvariant(addr);
719#endif
720}
721
722void
723Sequencer::recordRequestType(SequencerRequestType requestType) {
724    DPRINTF(RubyStats, "Recorded statistic: %s\n",
725            SequencerRequestType_to_string(requestType));
726}
727
728
729void
730Sequencer::evictionCallback(const Address& address)
731{
732    ruby_eviction_callback(address);
733}
734