Sequencer.cc revision 7039:bc0b6ea676b5 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "cpu/rubytest/RubyTester.hh"
30#include "mem/gems_common/Map.hh"
31#include "mem/protocol/CacheMsg.hh"
32#include "mem/protocol/Protocol.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/ruby/buffers/MessageBuffer.hh"
35#include "mem/ruby/common/Global.hh"
36#include "mem/ruby/common/SubBlock.hh"
37#include "mem/ruby/libruby.hh"
38#include "mem/ruby/profiler/Profiler.hh"
39#include "mem/ruby/recorder/Tracer.hh"
40#include "mem/ruby/slicc_interface/AbstractController.hh"
41#include "mem/ruby/system/CacheMemory.hh"
42#include "mem/ruby/system/Sequencer.hh"
43#include "mem/ruby/system/System.hh"
44#include "params/RubySequencer.hh"
45
46Sequencer *
47RubySequencerParams::create()
48{
49    return new Sequencer(this);
50}
51
52Sequencer::Sequencer(const Params *p)
53    : RubyPort(p), deadlockCheckEvent(this)
54{
55    m_store_waiting_on_load_cycles = 0;
56    m_store_waiting_on_store_cycles = 0;
57    m_load_waiting_on_store_cycles = 0;
58    m_load_waiting_on_load_cycles = 0;
59
60    m_outstanding_count = 0;
61
62    m_max_outstanding_requests = 0;
63    m_deadlock_threshold = 0;
64    m_instCache_ptr = NULL;
65    m_dataCache_ptr = NULL;
66
67    m_instCache_ptr = p->icache;
68    m_dataCache_ptr = p->dcache;
69    m_max_outstanding_requests = p->max_outstanding_requests;
70    m_deadlock_threshold = p->deadlock_threshold;
71    m_usingRubyTester = p->using_ruby_tester;
72
73    assert(m_max_outstanding_requests > 0);
74    assert(m_deadlock_threshold > 0);
75    assert(m_instCache_ptr != NULL);
76    assert(m_dataCache_ptr != NULL);
77}
78
79Sequencer::~Sequencer()
80{
81}
82
83void
84Sequencer::wakeup()
85{
86    // Check for deadlock of any of the requests
87    Time current_time = g_eventQueue_ptr->getTime();
88
89    // Check across all outstanding requests
90    int total_outstanding = 0;
91
92    Vector<Address> keys = m_readRequestTable.keys();
93    for (int i = 0; i < keys.size(); i++) {
94        SequencerRequest* request = m_readRequestTable.lookup(keys[i]);
95        if (current_time - request->issue_time >= m_deadlock_threshold) {
96            WARN_MSG("Possible Deadlock detected");
97            WARN_EXPR(request);
98            WARN_EXPR(m_version);
99            WARN_EXPR(request->ruby_request.paddr);
100            WARN_EXPR(keys.size());
101            WARN_EXPR(current_time);
102            WARN_EXPR(request->issue_time);
103            WARN_EXPR(current_time - request->issue_time);
104            ERROR_MSG("Aborting");
105        }
106    }
107
108    keys = m_writeRequestTable.keys();
109    for (int i = 0; i < keys.size(); i++) {
110        SequencerRequest* request = m_writeRequestTable.lookup(keys[i]);
111        if (current_time - request->issue_time >= m_deadlock_threshold) {
112            WARN_MSG("Possible Deadlock detected");
113            WARN_EXPR(request);
114            WARN_EXPR(m_version);
115            WARN_EXPR(current_time);
116            WARN_EXPR(request->issue_time);
117            WARN_EXPR(current_time - request->issue_time);
118            WARN_EXPR(keys.size());
119            ERROR_MSG("Aborting");
120        }
121    }
122
123    total_outstanding += m_writeRequestTable.size();
124    total_outstanding += m_readRequestTable.size();
125
126    assert(m_outstanding_count == total_outstanding);
127
128    if (m_outstanding_count > 0) {
129        // If there are still outstanding requests, keep checking
130        schedule(deadlockCheckEvent,
131                 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
132                 curTick);
133    }
134}
135
136void
137Sequencer::printStats(ostream & out) const
138{
139    out << "Sequencer: " << m_name << endl
140        << "  store_waiting_on_load_cycles: "
141        << m_store_waiting_on_load_cycles << endl
142        << "  store_waiting_on_store_cycles: "
143        << m_store_waiting_on_store_cycles << endl
144        << "  load_waiting_on_load_cycles: "
145        << m_load_waiting_on_load_cycles << endl
146        << "  load_waiting_on_store_cycles: "
147        << m_load_waiting_on_store_cycles << endl;
148}
149
150void
151Sequencer::printProgress(ostream& out) const
152{
153#if 0
154    int total_demand = 0;
155    out << "Sequencer Stats Version " << m_version << endl;
156    out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
157    out << "---------------" << endl;
158    out << "outstanding requests" << endl;
159
160    Vector<Address> rkeys = m_readRequestTable.keys();
161    int read_size = rkeys.size();
162    out << "proc " << m_version << " Read Requests = " << read_size << endl;
163
164    // print the request table
165    for (int i = 0; i < read_size; ++i) {
166        SequencerRequest *request = m_readRequestTable.lookup(rkeys[i]);
167        out << "\tRequest[ " << i << " ] = " << request->type
168            << " Address " << rkeys[i]
169            << " Posted " << request->issue_time
170            << " PF " << PrefetchBit_No << endl;
171        total_demand++;
172    }
173
174    Vector<Address> wkeys = m_writeRequestTable.keys();
175    int write_size = wkeys.size();
176    out << "proc " << m_version << " Write Requests = " << write_size << endl;
177
178    // print the request table
179    for (int i = 0; i < write_size; ++i){
180        CacheMsg &request = m_writeRequestTable.lookup(wkeys[i]);
181        out << "\tRequest[ " << i << " ] = " << request.getType()
182            << " Address " << wkeys[i]
183            << " Posted " << request.getTime()
184            << " PF " << request.getPrefetch() << endl;
185        if (request.getPrefetch() == PrefetchBit_No) {
186            total_demand++;
187        }
188    }
189
190    out << endl;
191
192    out << "Total Number Outstanding: " << m_outstanding_count << endl
193        << "Total Number Demand     : " << total_demand << endl
194        << "Total Number Prefetches : " << m_outstanding_count - total_demand
195        << endl << endl << endl;
196#endif
197}
198
199void
200Sequencer::printConfig(ostream& out) const
201{
202    out << "Seqeuncer config: " << m_name << endl
203        << "  controller: " << m_controller->getName() << endl
204        << "  version: " << m_version << endl
205        << "  max_outstanding_requests: " << m_max_outstanding_requests << endl
206        << "  deadlock_threshold: " << m_deadlock_threshold << endl;
207}
208
209// Insert the request on the correct request table.  Return true if
210// the entry was already present.
211bool
212Sequencer::insertRequest(SequencerRequest* request)
213{
214    int total_outstanding =
215        m_writeRequestTable.size() + m_readRequestTable.size();
216
217    assert(m_outstanding_count == total_outstanding);
218
219    // See if we should schedule a deadlock check
220    if (deadlockCheckEvent.scheduled() == false) {
221        schedule(deadlockCheckEvent, m_deadlock_threshold + curTick);
222    }
223
224    Address line_addr(request->ruby_request.paddr);
225    line_addr.makeLineAddress();
226    if ((request->ruby_request.type == RubyRequestType_ST) ||
227        (request->ruby_request.type == RubyRequestType_RMW_Read) ||
228        (request->ruby_request.type == RubyRequestType_RMW_Write) ||
229        (request->ruby_request.type == RubyRequestType_Locked_Read) ||
230        (request->ruby_request.type == RubyRequestType_Locked_Write)) {
231        if (m_writeRequestTable.exist(line_addr)) {
232            m_writeRequestTable.lookup(line_addr) = request;
233            // return true;
234
235            // drh5: isn't this an error?  do you lose the initial request?
236            assert(0);
237        }
238        m_writeRequestTable.allocate(line_addr);
239        m_writeRequestTable.lookup(line_addr) = request;
240        m_outstanding_count++;
241    } else {
242        if (m_readRequestTable.exist(line_addr)) {
243            m_readRequestTable.lookup(line_addr) = request;
244            // return true;
245
246            // drh5: isn't this an error?  do you lose the initial request?
247            assert(0);
248        }
249        m_readRequestTable.allocate(line_addr);
250        m_readRequestTable.lookup(line_addr) = request;
251        m_outstanding_count++;
252    }
253
254    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
255
256    total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
257    assert(m_outstanding_count == total_outstanding);
258
259    return false;
260}
261
262void
263Sequencer::removeRequest(SequencerRequest* srequest)
264{
265    assert(m_outstanding_count ==
266           m_writeRequestTable.size() + m_readRequestTable.size());
267
268    const RubyRequest & ruby_request = srequest->ruby_request;
269    Address line_addr(ruby_request.paddr);
270    line_addr.makeLineAddress();
271    if ((ruby_request.type == RubyRequestType_ST) ||
272        (ruby_request.type == RubyRequestType_RMW_Read) ||
273        (ruby_request.type == RubyRequestType_RMW_Write) ||
274        (ruby_request.type == RubyRequestType_Locked_Read) ||
275        (ruby_request.type == RubyRequestType_Locked_Write)) {
276        m_writeRequestTable.deallocate(line_addr);
277    } else {
278        m_readRequestTable.deallocate(line_addr);
279    }
280    m_outstanding_count--;
281
282    assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size());
283}
284
285void
286Sequencer::writeCallback(const Address& address, DataBlock& data)
287{
288    assert(address == line_address(address));
289    assert(m_writeRequestTable.exist(line_address(address)));
290
291    SequencerRequest* request = m_writeRequestTable.lookup(address);
292
293    removeRequest(request);
294
295    assert((request->ruby_request.type == RubyRequestType_ST) ||
296           (request->ruby_request.type == RubyRequestType_RMW_Read) ||
297           (request->ruby_request.type == RubyRequestType_RMW_Write) ||
298           (request->ruby_request.type == RubyRequestType_Locked_Read) ||
299           (request->ruby_request.type == RubyRequestType_Locked_Write));
300
301    if (request->ruby_request.type == RubyRequestType_Locked_Read) {
302        m_dataCache_ptr->setLocked(address, m_version);
303    } else if (request->ruby_request.type == RubyRequestType_RMW_Read) {
304        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
305    } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
306        m_controller->unblock(address);
307    }
308
309    hitCallback(request, data);
310}
311
312void
313Sequencer::readCallback(const Address& address, DataBlock& data)
314{
315    assert(address == line_address(address));
316    assert(m_readRequestTable.exist(line_address(address)));
317
318    SequencerRequest* request = m_readRequestTable.lookup(address);
319    removeRequest(request);
320
321    assert((request->ruby_request.type == RubyRequestType_LD) ||
322           (request->ruby_request.type == RubyRequestType_RMW_Read) ||
323           (request->ruby_request.type == RubyRequestType_IFETCH));
324
325    hitCallback(request, data);
326}
327
328void
329Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data)
330{
331    const RubyRequest & ruby_request = srequest->ruby_request;
332    Address request_address(ruby_request.paddr);
333    Address request_line_address(ruby_request.paddr);
334    request_line_address.makeLineAddress();
335    RubyRequestType type = ruby_request.type;
336    Time issued_time = srequest->issue_time;
337
338    // Set this cache entry to the most recently used
339    if (type == RubyRequestType_IFETCH) {
340        if (m_instCache_ptr->isTagPresent(request_line_address))
341            m_instCache_ptr->setMRU(request_line_address);
342    } else {
343        if (m_dataCache_ptr->isTagPresent(request_line_address))
344            m_dataCache_ptr->setMRU(request_line_address);
345    }
346
347    assert(g_eventQueue_ptr->getTime() >= issued_time);
348    Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
349
350    // Profile the miss latency for all non-zero demand misses
351    if (miss_latency != 0) {
352        g_system_ptr->getProfiler()->missLatency(miss_latency, type);
353
354        if (Debug::getProtocolTrace()) {
355            g_system_ptr->getProfiler()->
356                profileTransition("Seq", m_version,
357                                  Address(ruby_request.paddr), "", "Done", "",
358                                  csprintf("%d cycles", miss_latency));
359        }
360    }
361#if 0
362    if (request.getPrefetch() == PrefetchBit_Yes) {
363        return; // Ignore the prefetch
364    }
365#endif
366
367    // update the data
368    if (ruby_request.data != NULL) {
369        if ((type == RubyRequestType_LD) ||
370            (type == RubyRequestType_IFETCH) ||
371            (type == RubyRequestType_RMW_Read) ||
372            (type == RubyRequestType_Locked_Read)) {
373
374            memcpy(ruby_request.data,
375                   data.getData(request_address.getOffset(), ruby_request.len),
376                   ruby_request.len);
377        } else {
378            data.setData(ruby_request.data, request_address.getOffset(),
379                         ruby_request.len);
380        }
381    } else {
382        DPRINTF(MemoryAccess,
383                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
384                RubyRequestType_to_string(type));
385    }
386
387    // If using the RubyTester, update the RubyTester sender state's
388    // subBlock with the recieved data.  The tester will later access
389    // this state.
390    // Note: RubyPort will access it's sender state before the
391    // RubyTester.
392    if (m_usingRubyTester) {
393        RubyPort::SenderState *requestSenderState =
394            safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState);
395        RubyTester::SenderState* testerSenderState =
396            safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
397        testerSenderState->subBlock->mergeFrom(data);
398    }
399
400    ruby_hit_callback(ruby_request.pkt);
401    delete srequest;
402}
403
404// Returns true if the sequencer already has a load or store outstanding
405RequestStatus
406Sequencer::getRequestStatus(const RubyRequest& request)
407{
408    bool is_outstanding_store =
409        m_writeRequestTable.exist(line_address(Address(request.paddr)));
410    bool is_outstanding_load =
411        m_readRequestTable.exist(line_address(Address(request.paddr)));
412    if (is_outstanding_store) {
413        if ((request.type == RubyRequestType_LD) ||
414            (request.type == RubyRequestType_IFETCH) ||
415            (request.type == RubyRequestType_RMW_Read)) {
416            m_store_waiting_on_load_cycles++;
417        } else {
418            m_store_waiting_on_store_cycles++;
419        }
420        return RequestStatus_Aliased;
421    } else if (is_outstanding_load) {
422        if ((request.type == RubyRequestType_ST) ||
423            (request.type == RubyRequestType_RMW_Write)) {
424            m_load_waiting_on_store_cycles++;
425        } else {
426            m_load_waiting_on_load_cycles++;
427        }
428        return RequestStatus_Aliased;
429    }
430
431    if (m_outstanding_count >= m_max_outstanding_requests) {
432        return RequestStatus_BufferFull;
433    }
434
435    return RequestStatus_Ready;
436}
437
438bool
439Sequencer::empty() const
440{
441    return m_writeRequestTable.size() == 0 && m_readRequestTable.size() == 0;
442}
443
444RequestStatus
445Sequencer::makeRequest(const RubyRequest &request)
446{
447    assert(Address(request.paddr).getOffset() + request.len <=
448           RubySystem::getBlockSizeBytes());
449    RequestStatus status = getRequestStatus(request);
450    if (status != RequestStatus_Ready)
451        return status;
452
453    SequencerRequest *srequest =
454        new SequencerRequest(request, g_eventQueue_ptr->getTime());
455    bool found = insertRequest(srequest);
456    if (found) {
457        panic("Sequencer::makeRequest should never be called if the "
458              "request is already outstanding\n");
459        return RequestStatus_NULL;
460    }
461
462    if (request.type == RubyRequestType_Locked_Write) {
463        // NOTE: it is OK to check the locked flag here as the
464        // mandatory queue will be checked first ensuring that nothing
465        // comes between checking the flag and servicing the store.
466
467        Address line_addr = line_address(Address(request.paddr));
468        if (!m_dataCache_ptr->isLocked(line_addr, m_version)) {
469            removeRequest(srequest);
470            if (Debug::getProtocolTrace()) {
471                g_system_ptr->getProfiler()->
472                    profileTransition("Seq", m_version,
473                                      Address(request.paddr),
474                                      "", "SC Fail", "",
475                                      RubyRequestType_to_string(request.type));
476            }
477            return RequestStatus_LlscFailed;
478        } else {
479            m_dataCache_ptr->clearLocked(line_addr);
480        }
481    }
482    issueRequest(request);
483
484    // TODO: issue hardware prefetches here
485    return RequestStatus_Issued;
486}
487
488void
489Sequencer::issueRequest(const RubyRequest& request)
490{
491    // TODO: get rid of CacheMsg, CacheRequestType, and
492    // AccessModeTYpe, & have SLICC use RubyRequest and subtypes
493    // natively
494    CacheRequestType ctype;
495    switch(request.type) {
496      case RubyRequestType_IFETCH:
497        ctype = CacheRequestType_IFETCH;
498        break;
499      case RubyRequestType_LD:
500        ctype = CacheRequestType_LD;
501        break;
502      case RubyRequestType_ST:
503        ctype = CacheRequestType_ST;
504        break;
505      case RubyRequestType_Locked_Read:
506      case RubyRequestType_Locked_Write:
507        ctype = CacheRequestType_ATOMIC;
508        break;
509      case RubyRequestType_RMW_Read:
510        ctype = CacheRequestType_ATOMIC;
511        break;
512      case RubyRequestType_RMW_Write:
513        ctype = CacheRequestType_ATOMIC;
514        break;
515      default:
516        assert(0);
517    }
518
519    AccessModeType amtype;
520    switch(request.access_mode){
521      case RubyAccessMode_User:
522        amtype = AccessModeType_UserMode;
523        break;
524      case RubyAccessMode_Supervisor:
525        amtype = AccessModeType_SupervisorMode;
526        break;
527      case RubyAccessMode_Device:
528        amtype = AccessModeType_UserMode;
529        break;
530      default:
531        assert(0);
532    }
533
534    Address line_addr(request.paddr);
535    line_addr.makeLineAddress();
536    CacheMsg msg(line_addr, Address(request.paddr), ctype,
537                 Address(request.pc), amtype, request.len, PrefetchBit_No,
538                 request.proc_id);
539
540    if (Debug::getProtocolTrace()) {
541        g_system_ptr->getProfiler()->
542            profileTransition("Seq", m_version, Address(request.paddr),
543                              "", "Begin", "",
544                              RubyRequestType_to_string(request.type));
545    }
546
547    if (g_system_ptr->getTracer()->traceEnabled()) {
548        g_system_ptr->getTracer()->
549            traceRequest(this, line_addr, Address(request.pc),
550                         request.type, g_eventQueue_ptr->getTime());
551    }
552
553    Time latency = 0;  // initialzed to an null value
554
555    if (request.type == RubyRequestType_IFETCH)
556        latency = m_instCache_ptr->getLatency();
557    else
558        latency = m_dataCache_ptr->getLatency();
559
560    // Send the message to the cache controller
561    assert(latency > 0);
562
563    assert(m_mandatory_q_ptr != NULL);
564    m_mandatory_q_ptr->enqueue(msg, latency);
565}
566
567#if 0
568bool
569Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
570                          AccessModeType access_mode,
571                          int size, DataBlock*& data_ptr)
572{
573    CacheMemory *cache =
574        (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
575
576    return cache->tryCacheAccess(line_address(addr), type, data_ptr);
577}
578#endif
579
580void
581Sequencer::print(ostream& out) const
582{
583    out << "[Sequencer: " << m_version
584        << ", outstanding requests: " << m_outstanding_count
585        << ", read request table: " << m_readRequestTable
586        << ", write request table: " << m_writeRequestTable
587        << "]";
588}
589
590// this can be called from setState whenever coherence permissions are
591// upgraded when invoked, coherence violations will be checked for the
592// given block
593void
594Sequencer::checkCoherence(const Address& addr)
595{
596#ifdef CHECK_COHERENCE
597    g_system_ptr->checkGlobalCoherenceInvariant(addr);
598#endif
599}
600