Sequencer.cc revision 11019
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/x86/ldstflags.hh" 30#include "base/misc.hh" 31#include "base/str.hh" 32#include "cpu/testers/rubytest/RubyTester.hh" 33#include "debug/MemoryAccess.hh" 34#include "debug/ProtocolTrace.hh" 35#include "debug/RubySequencer.hh" 36#include "debug/RubyStats.hh" 37#include "mem/protocol/PrefetchBit.hh" 38#include "mem/protocol/RubyAccessMode.hh" 39#include "mem/ruby/profiler/Profiler.hh" 40#include "mem/ruby/slicc_interface/RubyRequest.hh" 41#include "mem/ruby/system/Sequencer.hh" 42#include "mem/ruby/system/System.hh" 43#include "mem/packet.hh" 44#include "sim/system.hh" 45 46using namespace std; 47 48Sequencer * 49RubySequencerParams::create() 50{ 51 return new Sequencer(this); 52} 53 54Sequencer::Sequencer(const Params *p) 55 : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this) 56{ 57 m_outstanding_count = 0; 58 59 m_instCache_ptr = p->icache; 60 m_dataCache_ptr = p->dcache; 61 m_data_cache_hit_latency = p->dcache_hit_latency; 62 m_inst_cache_hit_latency = p->icache_hit_latency; 63 m_max_outstanding_requests = p->max_outstanding_requests; 64 m_deadlock_threshold = p->deadlock_threshold; 65 66 assert(m_max_outstanding_requests > 0); 67 assert(m_deadlock_threshold > 0); 68 assert(m_instCache_ptr != NULL); 69 assert(m_dataCache_ptr != NULL); 70 assert(m_data_cache_hit_latency > 0); 71 assert(m_inst_cache_hit_latency > 0); 72 73 m_usingNetworkTester = p->using_network_tester; 74} 75 76Sequencer::~Sequencer() 77{ 78} 79 80void 81Sequencer::wakeup() 82{ 83 assert(drainState() != DrainState::Draining); 84 85 // Check for deadlock of any of the requests 86 Cycles current_time = curCycle(); 87 88 // Check across all outstanding requests 89 int total_outstanding = 0; 90 91 RequestTable::iterator read = m_readRequestTable.begin(); 92 RequestTable::iterator read_end = m_readRequestTable.end(); 93 for (; read != read_end; ++read) { 94 SequencerRequest* request = read->second; 95 if (current_time - request->issue_time < m_deadlock_threshold) 96 continue; 97 98 panic("Possible Deadlock detected. Aborting!\n" 99 "version: %d request.paddr: 0x%x m_readRequestTable: %d " 100 "current time: %u issue_time: %d difference: %d\n", m_version, 101 Address(request->pkt->getAddr()), m_readRequestTable.size(), 102 current_time * clockPeriod(), request->issue_time * clockPeriod(), 103 (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 104 } 105 106 RequestTable::iterator write = m_writeRequestTable.begin(); 107 RequestTable::iterator write_end = m_writeRequestTable.end(); 108 for (; write != write_end; ++write) { 109 SequencerRequest* request = write->second; 110 if (current_time - request->issue_time < m_deadlock_threshold) 111 continue; 112 113 panic("Possible Deadlock detected. Aborting!\n" 114 "version: %d request.paddr: 0x%x m_writeRequestTable: %d " 115 "current time: %u issue_time: %d difference: %d\n", m_version, 116 Address(request->pkt->getAddr()), m_writeRequestTable.size(), 117 current_time * clockPeriod(), request->issue_time * clockPeriod(), 118 (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 119 } 120 121 total_outstanding += m_writeRequestTable.size(); 122 total_outstanding += m_readRequestTable.size(); 123 124 assert(m_outstanding_count == total_outstanding); 125 126 if (m_outstanding_count > 0) { 127 // If there are still outstanding requests, keep checking 128 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 129 } 130} 131 132void Sequencer::resetStats() 133{ 134 m_latencyHist.reset(); 135 m_hitLatencyHist.reset(); 136 m_missLatencyHist.reset(); 137 for (int i = 0; i < RubyRequestType_NUM; i++) { 138 m_typeLatencyHist[i]->reset(); 139 m_hitTypeLatencyHist[i]->reset(); 140 m_missTypeLatencyHist[i]->reset(); 141 for (int j = 0; j < MachineType_NUM; j++) { 142 m_hitTypeMachLatencyHist[i][j]->reset(); 143 m_missTypeMachLatencyHist[i][j]->reset(); 144 } 145 } 146 147 for (int i = 0; i < MachineType_NUM; i++) { 148 m_missMachLatencyHist[i]->reset(); 149 m_hitMachLatencyHist[i]->reset(); 150 151 m_IssueToInitialDelayHist[i]->reset(); 152 m_InitialToForwardDelayHist[i]->reset(); 153 m_ForwardToFirstResponseDelayHist[i]->reset(); 154 m_FirstResponseToCompletionDelayHist[i]->reset(); 155 156 m_IncompleteTimes[i] = 0; 157 } 158} 159 160void 161Sequencer::printProgress(ostream& out) const 162{ 163#if 0 164 int total_demand = 0; 165 out << "Sequencer Stats Version " << m_version << endl; 166 out << "Current time = " << m_ruby_system->getTime() << endl; 167 out << "---------------" << endl; 168 out << "outstanding requests" << endl; 169 170 out << "proc " << m_Read 171 << " version Requests = " << m_readRequestTable.size() << endl; 172 173 // print the request table 174 RequestTable::iterator read = m_readRequestTable.begin(); 175 RequestTable::iterator read_end = m_readRequestTable.end(); 176 for (; read != read_end; ++read) { 177 SequencerRequest* request = read->second; 178 out << "\tRequest[ " << i << " ] = " << request->type 179 << " Address " << rkeys[i] 180 << " Posted " << request->issue_time 181 << " PF " << PrefetchBit_No << endl; 182 total_demand++; 183 } 184 185 out << "proc " << m_version 186 << " Write Requests = " << m_writeRequestTable.size << endl; 187 188 // print the request table 189 RequestTable::iterator write = m_writeRequestTable.begin(); 190 RequestTable::iterator write_end = m_writeRequestTable.end(); 191 for (; write != write_end; ++write) { 192 SequencerRequest* request = write->second; 193 out << "\tRequest[ " << i << " ] = " << request.getType() 194 << " Address " << wkeys[i] 195 << " Posted " << request.getTime() 196 << " PF " << request.getPrefetch() << endl; 197 if (request.getPrefetch() == PrefetchBit_No) { 198 total_demand++; 199 } 200 } 201 202 out << endl; 203 204 out << "Total Number Outstanding: " << m_outstanding_count << endl 205 << "Total Number Demand : " << total_demand << endl 206 << "Total Number Prefetches : " << m_outstanding_count - total_demand 207 << endl << endl << endl; 208#endif 209} 210 211// Insert the request on the correct request table. Return true if 212// the entry was already present. 213RequestStatus 214Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 215{ 216 assert(m_outstanding_count == 217 (m_writeRequestTable.size() + m_readRequestTable.size())); 218 219 // See if we should schedule a deadlock check 220 if (!deadlockCheckEvent.scheduled() && 221 drainState() != DrainState::Draining) { 222 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 223 } 224 225 Address line_addr(pkt->getAddr()); 226 line_addr.makeLineAddress(); 227 // Create a default entry, mapping the address to NULL, the cast is 228 // there to make gcc 4.4 happy 229 RequestTable::value_type default_entry(line_addr, 230 (SequencerRequest*) NULL); 231 232 if ((request_type == RubyRequestType_ST) || 233 (request_type == RubyRequestType_RMW_Read) || 234 (request_type == RubyRequestType_RMW_Write) || 235 (request_type == RubyRequestType_Load_Linked) || 236 (request_type == RubyRequestType_Store_Conditional) || 237 (request_type == RubyRequestType_Locked_RMW_Read) || 238 (request_type == RubyRequestType_Locked_RMW_Write) || 239 (request_type == RubyRequestType_FLUSH)) { 240 241 // Check if there is any outstanding read request for the same 242 // cache line. 243 if (m_readRequestTable.count(line_addr) > 0) { 244 m_store_waiting_on_load++; 245 return RequestStatus_Aliased; 246 } 247 248 pair<RequestTable::iterator, bool> r = 249 m_writeRequestTable.insert(default_entry); 250 if (r.second) { 251 RequestTable::iterator i = r.first; 252 i->second = new SequencerRequest(pkt, request_type, curCycle()); 253 m_outstanding_count++; 254 } else { 255 // There is an outstanding write request for the cache line 256 m_store_waiting_on_store++; 257 return RequestStatus_Aliased; 258 } 259 } else { 260 // Check if there is any outstanding write request for the same 261 // cache line. 262 if (m_writeRequestTable.count(line_addr) > 0) { 263 m_load_waiting_on_store++; 264 return RequestStatus_Aliased; 265 } 266 267 pair<RequestTable::iterator, bool> r = 268 m_readRequestTable.insert(default_entry); 269 270 if (r.second) { 271 RequestTable::iterator i = r.first; 272 i->second = new SequencerRequest(pkt, request_type, curCycle()); 273 m_outstanding_count++; 274 } else { 275 // There is an outstanding read request for the cache line 276 m_load_waiting_on_load++; 277 return RequestStatus_Aliased; 278 } 279 } 280 281 m_outstandReqHist.sample(m_outstanding_count); 282 assert(m_outstanding_count == 283 (m_writeRequestTable.size() + m_readRequestTable.size())); 284 285 return RequestStatus_Ready; 286} 287 288void 289Sequencer::markRemoved() 290{ 291 m_outstanding_count--; 292 assert(m_outstanding_count == 293 m_writeRequestTable.size() + m_readRequestTable.size()); 294} 295 296void 297Sequencer::removeRequest(SequencerRequest* srequest) 298{ 299 assert(m_outstanding_count == 300 m_writeRequestTable.size() + m_readRequestTable.size()); 301 302 Address line_addr(srequest->pkt->getAddr()); 303 line_addr.makeLineAddress(); 304 if ((srequest->m_type == RubyRequestType_ST) || 305 (srequest->m_type == RubyRequestType_RMW_Read) || 306 (srequest->m_type == RubyRequestType_RMW_Write) || 307 (srequest->m_type == RubyRequestType_Load_Linked) || 308 (srequest->m_type == RubyRequestType_Store_Conditional) || 309 (srequest->m_type == RubyRequestType_Locked_RMW_Read) || 310 (srequest->m_type == RubyRequestType_Locked_RMW_Write)) { 311 m_writeRequestTable.erase(line_addr); 312 } else { 313 m_readRequestTable.erase(line_addr); 314 } 315 316 markRemoved(); 317} 318 319void 320Sequencer::invalidateSC(const Address& address) 321{ 322 RequestTable::iterator i = m_writeRequestTable.find(address); 323 if (i != m_writeRequestTable.end()) { 324 SequencerRequest* request = i->second; 325 // The controller has lost the coherence permissions, hence the lock 326 // on the cache line maintained by the cache should be cleared. 327 if (request->m_type == RubyRequestType_Store_Conditional) { 328 m_dataCache_ptr->clearLocked(address); 329 } 330 } 331} 332 333bool 334Sequencer::handleLlsc(const Address& address, SequencerRequest* request) 335{ 336 // 337 // The success flag indicates whether the LLSC operation was successful. 338 // LL ops will always succeed, but SC may fail if the cache line is no 339 // longer locked. 340 // 341 bool success = true; 342 if (request->m_type == RubyRequestType_Store_Conditional) { 343 if (!m_dataCache_ptr->isLocked(address, m_version)) { 344 // 345 // For failed SC requests, indicate the failure to the cpu by 346 // setting the extra data to zero. 347 // 348 request->pkt->req->setExtraData(0); 349 success = false; 350 } else { 351 // 352 // For successful SC requests, indicate the success to the cpu by 353 // setting the extra data to one. 354 // 355 request->pkt->req->setExtraData(1); 356 } 357 // 358 // Independent of success, all SC operations must clear the lock 359 // 360 m_dataCache_ptr->clearLocked(address); 361 } else if (request->m_type == RubyRequestType_Load_Linked) { 362 // 363 // Note: To fully follow Alpha LLSC semantics, should the LL clear any 364 // previously locked cache lines? 365 // 366 m_dataCache_ptr->setLocked(address, m_version); 367 } else if ((m_dataCache_ptr->isTagPresent(address)) && 368 (m_dataCache_ptr->isLocked(address, m_version))) { 369 // 370 // Normal writes should clear the locked address 371 // 372 m_dataCache_ptr->clearLocked(address); 373 } 374 return success; 375} 376 377void 378Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 379 const MachineType respondingMach, 380 bool isExternalHit, Cycles issuedTime, 381 Cycles initialRequestTime, 382 Cycles forwardRequestTime, 383 Cycles firstResponseTime, Cycles completionTime) 384{ 385 m_latencyHist.sample(cycles); 386 m_typeLatencyHist[type]->sample(cycles); 387 388 if (isExternalHit) { 389 m_missLatencyHist.sample(cycles); 390 m_missTypeLatencyHist[type]->sample(cycles); 391 392 if (respondingMach != MachineType_NUM) { 393 m_missMachLatencyHist[respondingMach]->sample(cycles); 394 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles); 395 396 if ((issuedTime <= initialRequestTime) && 397 (initialRequestTime <= forwardRequestTime) && 398 (forwardRequestTime <= firstResponseTime) && 399 (firstResponseTime <= completionTime)) { 400 401 m_IssueToInitialDelayHist[respondingMach]->sample( 402 initialRequestTime - issuedTime); 403 m_InitialToForwardDelayHist[respondingMach]->sample( 404 forwardRequestTime - initialRequestTime); 405 m_ForwardToFirstResponseDelayHist[respondingMach]->sample( 406 firstResponseTime - forwardRequestTime); 407 m_FirstResponseToCompletionDelayHist[respondingMach]->sample( 408 completionTime - firstResponseTime); 409 } else { 410 m_IncompleteTimes[respondingMach]++; 411 } 412 } 413 } else { 414 m_hitLatencyHist.sample(cycles); 415 m_hitTypeLatencyHist[type]->sample(cycles); 416 417 if (respondingMach != MachineType_NUM) { 418 m_hitMachLatencyHist[respondingMach]->sample(cycles); 419 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles); 420 } 421 } 422} 423 424void 425Sequencer::writeCallback(const Address& address, DataBlock& data, 426 const bool externalHit, const MachineType mach, 427 const Cycles initialRequestTime, 428 const Cycles forwardRequestTime, 429 const Cycles firstResponseTime) 430{ 431 assert(address == line_address(address)); 432 assert(m_writeRequestTable.count(line_address(address))); 433 434 RequestTable::iterator i = m_writeRequestTable.find(address); 435 assert(i != m_writeRequestTable.end()); 436 SequencerRequest* request = i->second; 437 438 m_writeRequestTable.erase(i); 439 markRemoved(); 440 441 assert((request->m_type == RubyRequestType_ST) || 442 (request->m_type == RubyRequestType_ATOMIC) || 443 (request->m_type == RubyRequestType_RMW_Read) || 444 (request->m_type == RubyRequestType_RMW_Write) || 445 (request->m_type == RubyRequestType_Load_Linked) || 446 (request->m_type == RubyRequestType_Store_Conditional) || 447 (request->m_type == RubyRequestType_Locked_RMW_Read) || 448 (request->m_type == RubyRequestType_Locked_RMW_Write) || 449 (request->m_type == RubyRequestType_FLUSH)); 450 451 // 452 // For Alpha, properly handle LL, SC, and write requests with respect to 453 // locked cache blocks. 454 // 455 // Not valid for Network_test protocl 456 // 457 bool success = true; 458 if(!m_usingNetworkTester) 459 success = handleLlsc(address, request); 460 461 if (request->m_type == RubyRequestType_Locked_RMW_Read) { 462 m_controller->blockOnQueue(address, m_mandatory_q_ptr); 463 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { 464 m_controller->unblock(address); 465 } 466 467 hitCallback(request, data, success, mach, externalHit, 468 initialRequestTime, forwardRequestTime, firstResponseTime); 469} 470 471void 472Sequencer::readCallback(const Address& address, DataBlock& data, 473 bool externalHit, const MachineType mach, 474 Cycles initialRequestTime, 475 Cycles forwardRequestTime, 476 Cycles firstResponseTime) 477{ 478 assert(address == line_address(address)); 479 assert(m_readRequestTable.count(line_address(address))); 480 481 RequestTable::iterator i = m_readRequestTable.find(address); 482 assert(i != m_readRequestTable.end()); 483 SequencerRequest* request = i->second; 484 485 m_readRequestTable.erase(i); 486 markRemoved(); 487 488 assert((request->m_type == RubyRequestType_LD) || 489 (request->m_type == RubyRequestType_IFETCH)); 490 491 hitCallback(request, data, true, mach, externalHit, 492 initialRequestTime, forwardRequestTime, firstResponseTime); 493} 494 495void 496Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, 497 bool llscSuccess, 498 const MachineType mach, const bool externalHit, 499 const Cycles initialRequestTime, 500 const Cycles forwardRequestTime, 501 const Cycles firstResponseTime) 502{ 503 PacketPtr pkt = srequest->pkt; 504 Address request_address(pkt->getAddr()); 505 Address request_line_address(pkt->getAddr()); 506 request_line_address.makeLineAddress(); 507 RubyRequestType type = srequest->m_type; 508 Cycles issued_time = srequest->issue_time; 509 510 // Set this cache entry to the most recently used 511 if (type == RubyRequestType_IFETCH) { 512 m_instCache_ptr->setMRU(request_line_address); 513 } else { 514 m_dataCache_ptr->setMRU(request_line_address); 515 } 516 517 assert(curCycle() >= issued_time); 518 Cycles total_latency = curCycle() - issued_time; 519 520 // Profile the latency for all demand accesses. 521 recordMissLatency(total_latency, type, mach, externalHit, issued_time, 522 initialRequestTime, forwardRequestTime, 523 firstResponseTime, curCycle()); 524 525 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n", 526 curTick(), m_version, "Seq", 527 llscSuccess ? "Done" : "SC_Failed", "", "", 528 request_address, total_latency); 529 530 // update the data unless it is a non-data-carrying flush 531 if (RubySystem::getWarmupEnabled()) { 532 data.setData(pkt->getConstPtr<uint8_t>(), 533 request_address.getOffset(), pkt->getSize()); 534 } else if (!pkt->isFlush()) { 535 if ((type == RubyRequestType_LD) || 536 (type == RubyRequestType_IFETCH) || 537 (type == RubyRequestType_RMW_Read) || 538 (type == RubyRequestType_Locked_RMW_Read) || 539 (type == RubyRequestType_Load_Linked)) { 540 memcpy(pkt->getPtr<uint8_t>(), 541 data.getData(request_address.getOffset(), pkt->getSize()), 542 pkt->getSize()); 543 DPRINTF(RubySequencer, "read data %s\n", data); 544 } else { 545 data.setData(pkt->getConstPtr<uint8_t>(), 546 request_address.getOffset(), pkt->getSize()); 547 DPRINTF(RubySequencer, "set data %s\n", data); 548 } 549 } 550 551 // If using the RubyTester, update the RubyTester sender state's 552 // subBlock with the recieved data. The tester will later access 553 // this state. 554 if (m_usingRubyTester) { 555 DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n", 556 pkt->cmdString(), pkt->getAddr()); 557 RubyTester::SenderState* testerSenderState = 558 pkt->findNextSenderState<RubyTester::SenderState>(); 559 assert(testerSenderState); 560 testerSenderState->subBlock.mergeFrom(data); 561 } 562 563 delete srequest; 564 565 RubySystem *rs = m_ruby_system; 566 if (RubySystem::getWarmupEnabled()) { 567 assert(pkt->req); 568 delete pkt->req; 569 delete pkt; 570 rs->m_cache_recorder->enqueueNextFetchRequest(); 571 } else if (RubySystem::getCooldownEnabled()) { 572 delete pkt; 573 rs->m_cache_recorder->enqueueNextFlushRequest(); 574 } else { 575 ruby_hit_callback(pkt); 576 } 577} 578 579bool 580Sequencer::empty() const 581{ 582 return m_writeRequestTable.empty() && m_readRequestTable.empty(); 583} 584 585RequestStatus 586Sequencer::makeRequest(PacketPtr pkt) 587{ 588 if (m_outstanding_count >= m_max_outstanding_requests) { 589 return RequestStatus_BufferFull; 590 } 591 592 RubyRequestType primary_type = RubyRequestType_NULL; 593 RubyRequestType secondary_type = RubyRequestType_NULL; 594 595 if (pkt->isLLSC()) { 596 // 597 // Alpha LL/SC instructions need to be handled carefully by the cache 598 // coherence protocol to ensure they follow the proper semantics. In 599 // particular, by identifying the operations as atomic, the protocol 600 // should understand that migratory sharing optimizations should not 601 // be performed (i.e. a load between the LL and SC should not steal 602 // away exclusive permission). 603 // 604 if (pkt->isWrite()) { 605 DPRINTF(RubySequencer, "Issuing SC\n"); 606 primary_type = RubyRequestType_Store_Conditional; 607 } else { 608 DPRINTF(RubySequencer, "Issuing LL\n"); 609 assert(pkt->isRead()); 610 primary_type = RubyRequestType_Load_Linked; 611 } 612 secondary_type = RubyRequestType_ATOMIC; 613 } else if (pkt->req->isLockedRMW()) { 614 // 615 // x86 locked instructions are translated to store cache coherence 616 // requests because these requests should always be treated as read 617 // exclusive operations and should leverage any migratory sharing 618 // optimization built into the protocol. 619 // 620 if (pkt->isWrite()) { 621 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); 622 primary_type = RubyRequestType_Locked_RMW_Write; 623 } else { 624 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); 625 assert(pkt->isRead()); 626 primary_type = RubyRequestType_Locked_RMW_Read; 627 } 628 secondary_type = RubyRequestType_ST; 629 } else { 630 if (pkt->isRead()) { 631 if (pkt->req->isInstFetch()) { 632 primary_type = secondary_type = RubyRequestType_IFETCH; 633 } else { 634 bool storeCheck = false; 635 // only X86 need the store check 636 if (system->getArch() == Arch::X86ISA) { 637 uint32_t flags = pkt->req->getFlags(); 638 storeCheck = flags & 639 (X86ISA::StoreCheck << X86ISA::FlagShift); 640 } 641 if (storeCheck) { 642 primary_type = RubyRequestType_RMW_Read; 643 secondary_type = RubyRequestType_ST; 644 } else { 645 primary_type = secondary_type = RubyRequestType_LD; 646 } 647 } 648 } else if (pkt->isWrite()) { 649 // 650 // Note: M5 packets do not differentiate ST from RMW_Write 651 // 652 primary_type = secondary_type = RubyRequestType_ST; 653 } else if (pkt->isFlush()) { 654 primary_type = secondary_type = RubyRequestType_FLUSH; 655 } else { 656 panic("Unsupported ruby packet type\n"); 657 } 658 } 659 660 RequestStatus status = insertRequest(pkt, primary_type); 661 if (status != RequestStatus_Ready) 662 return status; 663 664 issueRequest(pkt, secondary_type); 665 666 // TODO: issue hardware prefetches here 667 return RequestStatus_Issued; 668} 669 670void 671Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) 672{ 673 assert(pkt != NULL); 674 ContextID proc_id = pkt->req->hasContextId() ? 675 pkt->req->contextId() : InvalidContextID; 676 677 // If valid, copy the pc to the ruby request 678 Addr pc = 0; 679 if (pkt->req->hasPC()) { 680 pc = pkt->req->getPC(); 681 } 682 683 // check if the packet has data as for example prefetch and flush 684 // requests do not 685 std::shared_ptr<RubyRequest> msg = 686 std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(), 687 pkt->isFlush() ? 688 nullptr : pkt->getPtr<uint8_t>(), 689 pkt->getSize(), pc, secondary_type, 690 RubyAccessMode_Supervisor, pkt, 691 PrefetchBit_No, proc_id); 692 693 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n", 694 curTick(), m_version, "Seq", "Begin", "", "", 695 msg->getPhysicalAddress(), 696 RubyRequestType_to_string(secondary_type)); 697 698 // The Sequencer currently assesses instruction and data cache hit latency 699 // for the top-level caches at the beginning of a memory access. 700 // TODO: Eventually, this latency should be moved to represent the actual 701 // cache access latency portion of the memory access. This will require 702 // changing cache controller protocol files to assess the latency on the 703 // access response path. 704 Cycles latency(0); // Initialize to zero to catch misconfigured latency 705 if (secondary_type == RubyRequestType_IFETCH) 706 latency = m_inst_cache_hit_latency; 707 else 708 latency = m_data_cache_hit_latency; 709 710 // Send the message to the cache controller 711 assert(latency > 0); 712 713 assert(m_mandatory_q_ptr != NULL); 714 m_mandatory_q_ptr->enqueue(msg, latency); 715} 716 717template <class KEY, class VALUE> 718std::ostream & 719operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) 720{ 721 typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); 722 typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); 723 724 out << "["; 725 for (; i != end; ++i) 726 out << " " << i->first << "=" << i->second; 727 out << " ]"; 728 729 return out; 730} 731 732void 733Sequencer::print(ostream& out) const 734{ 735 out << "[Sequencer: " << m_version 736 << ", outstanding requests: " << m_outstanding_count 737 << ", read request table: " << m_readRequestTable 738 << ", write request table: " << m_writeRequestTable 739 << "]"; 740} 741 742// this can be called from setState whenever coherence permissions are 743// upgraded when invoked, coherence violations will be checked for the 744// given block 745void 746Sequencer::checkCoherence(const Address& addr) 747{ 748#ifdef CHECK_COHERENCE 749 m_ruby_system->checkGlobalCoherenceInvariant(addr); 750#endif 751} 752 753void 754Sequencer::recordRequestType(SequencerRequestType requestType) { 755 DPRINTF(RubyStats, "Recorded statistic: %s\n", 756 SequencerRequestType_to_string(requestType)); 757} 758 759 760void 761Sequencer::evictionCallback(const Address& address) 762{ 763 ruby_eviction_callback(address); 764} 765 766void 767Sequencer::regStats() 768{ 769 m_store_waiting_on_load 770 .name(name() + ".store_waiting_on_load") 771 .desc("Number of times a store aliased with a pending load") 772 .flags(Stats::nozero); 773 m_store_waiting_on_store 774 .name(name() + ".store_waiting_on_store") 775 .desc("Number of times a store aliased with a pending store") 776 .flags(Stats::nozero); 777 m_load_waiting_on_load 778 .name(name() + ".load_waiting_on_load") 779 .desc("Number of times a load aliased with a pending load") 780 .flags(Stats::nozero); 781 m_load_waiting_on_store 782 .name(name() + ".load_waiting_on_store") 783 .desc("Number of times a load aliased with a pending store") 784 .flags(Stats::nozero); 785 786 // These statistical variables are not for display. 787 // The profiler will collate these across different 788 // sequencers and display those collated statistics. 789 m_outstandReqHist.init(10); 790 m_latencyHist.init(10); 791 m_hitLatencyHist.init(10); 792 m_missLatencyHist.init(10); 793 794 for (int i = 0; i < RubyRequestType_NUM; i++) { 795 m_typeLatencyHist.push_back(new Stats::Histogram()); 796 m_typeLatencyHist[i]->init(10); 797 798 m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 799 m_hitTypeLatencyHist[i]->init(10); 800 801 m_missTypeLatencyHist.push_back(new Stats::Histogram()); 802 m_missTypeLatencyHist[i]->init(10); 803 } 804 805 for (int i = 0; i < MachineType_NUM; i++) { 806 m_hitMachLatencyHist.push_back(new Stats::Histogram()); 807 m_hitMachLatencyHist[i]->init(10); 808 809 m_missMachLatencyHist.push_back(new Stats::Histogram()); 810 m_missMachLatencyHist[i]->init(10); 811 812 m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 813 m_IssueToInitialDelayHist[i]->init(10); 814 815 m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 816 m_InitialToForwardDelayHist[i]->init(10); 817 818 m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 819 m_ForwardToFirstResponseDelayHist[i]->init(10); 820 821 m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 822 m_FirstResponseToCompletionDelayHist[i]->init(10); 823 } 824 825 for (int i = 0; i < RubyRequestType_NUM; i++) { 826 m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 827 m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 828 829 for (int j = 0; j < MachineType_NUM; j++) { 830 m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 831 m_hitTypeMachLatencyHist[i][j]->init(10); 832 833 m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 834 m_missTypeMachLatencyHist[i][j]->init(10); 835 } 836 } 837} 838