Sequencer.cc revision 11321
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org */ 286145Snate@binkert.org 2910467Sandreas.hansson@arm.com#include "arch/x86/ldstflags.hh" 308229Snate@binkert.org#include "base/misc.hh" 317056Snate@binkert.org#include "base/str.hh" 327632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 338232Snate@binkert.org#include "debug/MemoryAccess.hh" 348232Snate@binkert.org#include "debug/ProtocolTrace.hh" 358615Snilay@cs.wisc.edu#include "debug/RubySequencer.hh" 369104Shestness@cs.utexas.edu#include "debug/RubyStats.hh" 378615Snilay@cs.wisc.edu#include "mem/protocol/PrefetchBit.hh" 388615Snilay@cs.wisc.edu#include "mem/protocol/RubyAccessMode.hh" 397039Snate@binkert.org#include "mem/ruby/profiler/Profiler.hh" 408229Snate@binkert.org#include "mem/ruby/slicc_interface/RubyRequest.hh" 4111108Sdavid.hashe@amd.com#include "mem/ruby/system/RubySystem.hh" 426154Snate@binkert.org#include "mem/ruby/system/Sequencer.hh" 437550SBrad.Beckmann@amd.com#include "mem/packet.hh" 4410467Sandreas.hansson@arm.com#include "sim/system.hh" 456876Ssteve.reinhardt@amd.com 467055Snate@binkert.orgusing namespace std; 477055Snate@binkert.org 486876Ssteve.reinhardt@amd.comSequencer * 496876Ssteve.reinhardt@amd.comRubySequencerParams::create() 506285Snate@binkert.org{ 516876Ssteve.reinhardt@amd.com return new Sequencer(this); 526285Snate@binkert.org} 537039Snate@binkert.org 546876Ssteve.reinhardt@amd.comSequencer::Sequencer(const Params *p) 5510012Snilay@cs.wisc.edu : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this) 566876Ssteve.reinhardt@amd.com{ 576876Ssteve.reinhardt@amd.com m_outstanding_count = 0; 586285Snate@binkert.org 596876Ssteve.reinhardt@amd.com m_instCache_ptr = p->icache; 606876Ssteve.reinhardt@amd.com m_dataCache_ptr = p->dcache; 6111019Sjthestness@gmail.com m_data_cache_hit_latency = p->dcache_hit_latency; 6211019Sjthestness@gmail.com m_inst_cache_hit_latency = p->icache_hit_latency; 636876Ssteve.reinhardt@amd.com m_max_outstanding_requests = p->max_outstanding_requests; 646876Ssteve.reinhardt@amd.com m_deadlock_threshold = p->deadlock_threshold; 656899SBrad.Beckmann@amd.com 6611308Santhony.gutierrez@amd.com m_coreId = p->coreid; // for tracking the two CorePair sequencers 676876Ssteve.reinhardt@amd.com assert(m_max_outstanding_requests > 0); 686876Ssteve.reinhardt@amd.com assert(m_deadlock_threshold > 0); 696876Ssteve.reinhardt@amd.com assert(m_instCache_ptr != NULL); 706876Ssteve.reinhardt@amd.com assert(m_dataCache_ptr != NULL); 7111019Sjthestness@gmail.com assert(m_data_cache_hit_latency > 0); 7211019Sjthestness@gmail.com assert(m_inst_cache_hit_latency > 0); 738171Stushar@csail.mit.edu 748171Stushar@csail.mit.edu m_usingNetworkTester = p->using_network_tester; 756145Snate@binkert.org} 766145Snate@binkert.org 777039Snate@binkert.orgSequencer::~Sequencer() 787039Snate@binkert.org{ 796145Snate@binkert.org} 806145Snate@binkert.org 817039Snate@binkert.orgvoid 827039Snate@binkert.orgSequencer::wakeup() 837039Snate@binkert.org{ 8410913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Draining); 859245Shestness@cs.wisc.edu 867039Snate@binkert.org // Check for deadlock of any of the requests 879501Snilay@cs.wisc.edu Cycles current_time = curCycle(); 886145Snate@binkert.org 897039Snate@binkert.org // Check across all outstanding requests 907039Snate@binkert.org int total_outstanding = 0; 916285Snate@binkert.org 927455Snate@binkert.org RequestTable::iterator read = m_readRequestTable.begin(); 937455Snate@binkert.org RequestTable::iterator read_end = m_readRequestTable.end(); 947455Snate@binkert.org for (; read != read_end; ++read) { 957455Snate@binkert.org SequencerRequest* request = read->second; 967455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 977455Snate@binkert.org continue; 987455Snate@binkert.org 997805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 10011025Snilay@cs.wisc.edu "version: %d request.paddr: 0x%x m_readRequestTable: %d " 10111025Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 10211025Snilay@cs.wisc.edu request->pkt->getAddr(), m_readRequestTable.size(), 1039467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1049467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1056145Snate@binkert.org } 1066145Snate@binkert.org 1077455Snate@binkert.org RequestTable::iterator write = m_writeRequestTable.begin(); 1087455Snate@binkert.org RequestTable::iterator write_end = m_writeRequestTable.end(); 1097455Snate@binkert.org for (; write != write_end; ++write) { 1107455Snate@binkert.org SequencerRequest* request = write->second; 1117455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 1127455Snate@binkert.org continue; 1137455Snate@binkert.org 1147805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 11511025Snilay@cs.wisc.edu "version: %d request.paddr: 0x%x m_writeRequestTable: %d " 11611025Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 11711025Snilay@cs.wisc.edu request->pkt->getAddr(), m_writeRequestTable.size(), 1189467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1199467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1206145Snate@binkert.org } 1216285Snate@binkert.org 1227039Snate@binkert.org total_outstanding += m_writeRequestTable.size(); 1237039Snate@binkert.org total_outstanding += m_readRequestTable.size(); 1246145Snate@binkert.org 1257039Snate@binkert.org assert(m_outstanding_count == total_outstanding); 1267039Snate@binkert.org 1277039Snate@binkert.org if (m_outstanding_count > 0) { 1287039Snate@binkert.org // If there are still outstanding requests, keep checking 1299465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 1307039Snate@binkert.org } 1316145Snate@binkert.org} 1326145Snate@binkert.org 13310012Snilay@cs.wisc.eduvoid Sequencer::resetStats() 1349598Snilay@cs.wisc.edu{ 13510012Snilay@cs.wisc.edu m_latencyHist.reset(); 13610012Snilay@cs.wisc.edu m_hitLatencyHist.reset(); 13710012Snilay@cs.wisc.edu m_missLatencyHist.reset(); 1389773Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 13910012Snilay@cs.wisc.edu m_typeLatencyHist[i]->reset(); 14010012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->reset(); 14110012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->reset(); 1429773Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 14310012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->reset(); 14410012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->reset(); 1459773Snilay@cs.wisc.edu } 1469773Snilay@cs.wisc.edu } 1479773Snilay@cs.wisc.edu 14810012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 14910012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->reset(); 15010012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->reset(); 1519773Snilay@cs.wisc.edu 15210012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->reset(); 15310012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->reset(); 15410012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->reset(); 15510012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->reset(); 1569773Snilay@cs.wisc.edu 1579773Snilay@cs.wisc.edu m_IncompleteTimes[i] = 0; 1589773Snilay@cs.wisc.edu } 1599598Snilay@cs.wisc.edu} 1609598Snilay@cs.wisc.edu 1616145Snate@binkert.org// Insert the request on the correct request table. Return true if 1626145Snate@binkert.org// the entry was already present. 1638615Snilay@cs.wisc.eduRequestStatus 1648615Snilay@cs.wisc.eduSequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 1657039Snate@binkert.org{ 1668641Snate@binkert.org assert(m_outstanding_count == 1678641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 1686145Snate@binkert.org 1697039Snate@binkert.org // See if we should schedule a deadlock check 1709342SAndreas.Sandberg@arm.com if (!deadlockCheckEvent.scheduled() && 17110913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) { 1729465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 1737039Snate@binkert.org } 1746145Snate@binkert.org 17511025Snilay@cs.wisc.edu Addr line_addr = makeLineAddress(pkt->getAddr()); 1769224Sandreas.hansson@arm.com // Create a default entry, mapping the address to NULL, the cast is 1779224Sandreas.hansson@arm.com // there to make gcc 4.4 happy 1789224Sandreas.hansson@arm.com RequestTable::value_type default_entry(line_addr, 1799224Sandreas.hansson@arm.com (SequencerRequest*) NULL); 1809224Sandreas.hansson@arm.com 1818615Snilay@cs.wisc.edu if ((request_type == RubyRequestType_ST) || 1828615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Read) || 1838615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Write) || 1848615Snilay@cs.wisc.edu (request_type == RubyRequestType_Load_Linked) || 1858615Snilay@cs.wisc.edu (request_type == RubyRequestType_Store_Conditional) || 1868615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Read) || 1878615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Write) || 1888615Snilay@cs.wisc.edu (request_type == RubyRequestType_FLUSH)) { 1898615Snilay@cs.wisc.edu 1908615Snilay@cs.wisc.edu // Check if there is any outstanding read request for the same 1918615Snilay@cs.wisc.edu // cache line. 1928615Snilay@cs.wisc.edu if (m_readRequestTable.count(line_addr) > 0) { 19310012Snilay@cs.wisc.edu m_store_waiting_on_load++; 1948615Snilay@cs.wisc.edu return RequestStatus_Aliased; 1958615Snilay@cs.wisc.edu } 1968615Snilay@cs.wisc.edu 1977455Snate@binkert.org pair<RequestTable::iterator, bool> r = 1989224Sandreas.hansson@arm.com m_writeRequestTable.insert(default_entry); 1998615Snilay@cs.wisc.edu if (r.second) { 2008615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2019465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2028615Snilay@cs.wisc.edu m_outstanding_count++; 2038615Snilay@cs.wisc.edu } else { 2048615Snilay@cs.wisc.edu // There is an outstanding write request for the cache line 20510012Snilay@cs.wisc.edu m_store_waiting_on_store++; 2068615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2078615Snilay@cs.wisc.edu } 2088615Snilay@cs.wisc.edu } else { 2098615Snilay@cs.wisc.edu // Check if there is any outstanding write request for the same 2108615Snilay@cs.wisc.edu // cache line. 2118615Snilay@cs.wisc.edu if (m_writeRequestTable.count(line_addr) > 0) { 21210012Snilay@cs.wisc.edu m_load_waiting_on_store++; 2138615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2148615Snilay@cs.wisc.edu } 2157039Snate@binkert.org 2167455Snate@binkert.org pair<RequestTable::iterator, bool> r = 2179224Sandreas.hansson@arm.com m_readRequestTable.insert(default_entry); 2187039Snate@binkert.org 2198615Snilay@cs.wisc.edu if (r.second) { 2208615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2219465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2228615Snilay@cs.wisc.edu m_outstanding_count++; 2238615Snilay@cs.wisc.edu } else { 2248615Snilay@cs.wisc.edu // There is an outstanding read request for the cache line 22510012Snilay@cs.wisc.edu m_load_waiting_on_load++; 2268615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2277039Snate@binkert.org } 2286145Snate@binkert.org } 2296145Snate@binkert.org 23010012Snilay@cs.wisc.edu m_outstandReqHist.sample(m_outstanding_count); 2318641Snate@binkert.org assert(m_outstanding_count == 2328641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 2336145Snate@binkert.org 2348615Snilay@cs.wisc.edu return RequestStatus_Ready; 2356145Snate@binkert.org} 2366145Snate@binkert.org 2377039Snate@binkert.orgvoid 2387455Snate@binkert.orgSequencer::markRemoved() 2397455Snate@binkert.org{ 2407455Snate@binkert.org m_outstanding_count--; 2417455Snate@binkert.org assert(m_outstanding_count == 2427455Snate@binkert.org m_writeRequestTable.size() + m_readRequestTable.size()); 2437455Snate@binkert.org} 2447455Snate@binkert.org 2457455Snate@binkert.orgvoid 24611025Snilay@cs.wisc.eduSequencer::invalidateSC(Addr address) 2479563Sgope@wisc.edu{ 24811059Snilay@cs.wisc.edu AbstractCacheEntry *e = m_dataCache_ptr->lookup(address); 24911059Snilay@cs.wisc.edu // The controller has lost the coherence permissions, hence the lock 25011059Snilay@cs.wisc.edu // on the cache line maintained by the cache should be cleared. 25111059Snilay@cs.wisc.edu if (e && e->isLocked(m_version)) { 25211059Snilay@cs.wisc.edu e->clearLocked(); 2539563Sgope@wisc.edu } 2549563Sgope@wisc.edu} 2559563Sgope@wisc.edu 2567560SBrad.Beckmann@amd.combool 25711025Snilay@cs.wisc.eduSequencer::handleLlsc(Addr address, SequencerRequest* request) 2587550SBrad.Beckmann@amd.com{ 25911059Snilay@cs.wisc.edu AbstractCacheEntry *e = m_dataCache_ptr->lookup(address); 26011059Snilay@cs.wisc.edu if (!e) 26111059Snilay@cs.wisc.edu return true; 26211059Snilay@cs.wisc.edu 2637560SBrad.Beckmann@amd.com // The success flag indicates whether the LLSC operation was successful. 2647560SBrad.Beckmann@amd.com // LL ops will always succeed, but SC may fail if the cache line is no 2657560SBrad.Beckmann@amd.com // longer locked. 2667560SBrad.Beckmann@amd.com bool success = true; 2678615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Store_Conditional) { 26811059Snilay@cs.wisc.edu if (!e->isLocked(m_version)) { 2697550SBrad.Beckmann@amd.com // 2707550SBrad.Beckmann@amd.com // For failed SC requests, indicate the failure to the cpu by 2717550SBrad.Beckmann@amd.com // setting the extra data to zero. 2727550SBrad.Beckmann@amd.com // 2738615Snilay@cs.wisc.edu request->pkt->req->setExtraData(0); 2747560SBrad.Beckmann@amd.com success = false; 2757550SBrad.Beckmann@amd.com } else { 2767550SBrad.Beckmann@amd.com // 2777550SBrad.Beckmann@amd.com // For successful SC requests, indicate the success to the cpu by 27810917Sbrandon.potter@amd.com // setting the extra data to one. 2797550SBrad.Beckmann@amd.com // 2808615Snilay@cs.wisc.edu request->pkt->req->setExtraData(1); 2817550SBrad.Beckmann@amd.com } 2827560SBrad.Beckmann@amd.com // 2837560SBrad.Beckmann@amd.com // Independent of success, all SC operations must clear the lock 2847560SBrad.Beckmann@amd.com // 28511059Snilay@cs.wisc.edu e->clearLocked(); 2868615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Load_Linked) { 2877550SBrad.Beckmann@amd.com // 2887550SBrad.Beckmann@amd.com // Note: To fully follow Alpha LLSC semantics, should the LL clear any 2897550SBrad.Beckmann@amd.com // previously locked cache lines? 2907550SBrad.Beckmann@amd.com // 29111059Snilay@cs.wisc.edu e->setLocked(m_version); 29211059Snilay@cs.wisc.edu } else if (e->isLocked(m_version)) { 2937550SBrad.Beckmann@amd.com // 2947550SBrad.Beckmann@amd.com // Normal writes should clear the locked address 2957550SBrad.Beckmann@amd.com // 29611059Snilay@cs.wisc.edu e->clearLocked(); 2977550SBrad.Beckmann@amd.com } 2987560SBrad.Beckmann@amd.com return success; 2997550SBrad.Beckmann@amd.com} 3007550SBrad.Beckmann@amd.com 3017550SBrad.Beckmann@amd.comvoid 3029773Snilay@cs.wisc.eduSequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 3039773Snilay@cs.wisc.edu const MachineType respondingMach, 3049773Snilay@cs.wisc.edu bool isExternalHit, Cycles issuedTime, 3059773Snilay@cs.wisc.edu Cycles initialRequestTime, 3069773Snilay@cs.wisc.edu Cycles forwardRequestTime, 3079773Snilay@cs.wisc.edu Cycles firstResponseTime, Cycles completionTime) 3087039Snate@binkert.org{ 30910012Snilay@cs.wisc.edu m_latencyHist.sample(cycles); 31010012Snilay@cs.wisc.edu m_typeLatencyHist[type]->sample(cycles); 3119773Snilay@cs.wisc.edu 3129773Snilay@cs.wisc.edu if (isExternalHit) { 31310012Snilay@cs.wisc.edu m_missLatencyHist.sample(cycles); 31410012Snilay@cs.wisc.edu m_missTypeLatencyHist[type]->sample(cycles); 3159773Snilay@cs.wisc.edu 3169773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 31710012Snilay@cs.wisc.edu m_missMachLatencyHist[respondingMach]->sample(cycles); 31810012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles); 3199773Snilay@cs.wisc.edu 3209773Snilay@cs.wisc.edu if ((issuedTime <= initialRequestTime) && 3219773Snilay@cs.wisc.edu (initialRequestTime <= forwardRequestTime) && 3229773Snilay@cs.wisc.edu (forwardRequestTime <= firstResponseTime) && 3239773Snilay@cs.wisc.edu (firstResponseTime <= completionTime)) { 3249773Snilay@cs.wisc.edu 32510012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[respondingMach]->sample( 3269773Snilay@cs.wisc.edu initialRequestTime - issuedTime); 32710012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[respondingMach]->sample( 3289773Snilay@cs.wisc.edu forwardRequestTime - initialRequestTime); 32910012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[respondingMach]->sample( 3309773Snilay@cs.wisc.edu firstResponseTime - forwardRequestTime); 33110012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[respondingMach]->sample( 3329773Snilay@cs.wisc.edu completionTime - firstResponseTime); 3339773Snilay@cs.wisc.edu } else { 3349773Snilay@cs.wisc.edu m_IncompleteTimes[respondingMach]++; 3359773Snilay@cs.wisc.edu } 3369773Snilay@cs.wisc.edu } 3379773Snilay@cs.wisc.edu } else { 33810012Snilay@cs.wisc.edu m_hitLatencyHist.sample(cycles); 33910012Snilay@cs.wisc.edu m_hitTypeLatencyHist[type]->sample(cycles); 3409773Snilay@cs.wisc.edu 3419773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 34210012Snilay@cs.wisc.edu m_hitMachLatencyHist[respondingMach]->sample(cycles); 34310012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles); 3449773Snilay@cs.wisc.edu } 3459773Snilay@cs.wisc.edu } 3467546SBrad.Beckmann@amd.com} 3477546SBrad.Beckmann@amd.com 3487546SBrad.Beckmann@amd.comvoid 34911025Snilay@cs.wisc.eduSequencer::writeCallback(Addr address, DataBlock& data, 3509773Snilay@cs.wisc.edu const bool externalHit, const MachineType mach, 3519773Snilay@cs.wisc.edu const Cycles initialRequestTime, 3529773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 3539773Snilay@cs.wisc.edu const Cycles firstResponseTime) 3547565SBrad.Beckmann@amd.com{ 35511025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 35611025Snilay@cs.wisc.edu assert(m_writeRequestTable.count(makeLineAddress(address))); 3576145Snate@binkert.org 3587455Snate@binkert.org RequestTable::iterator i = m_writeRequestTable.find(address); 3597455Snate@binkert.org assert(i != m_writeRequestTable.end()); 3607455Snate@binkert.org SequencerRequest* request = i->second; 3616145Snate@binkert.org 3627455Snate@binkert.org m_writeRequestTable.erase(i); 3637455Snate@binkert.org markRemoved(); 3646846Spdudnik@cs.wisc.edu 3658615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_ST) || 3668615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_ATOMIC) || 3678615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Read) || 3688615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Write) || 3698615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Load_Linked) || 3708615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Store_Conditional) || 3718615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Read) || 3728615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Write) || 3738615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_FLUSH)); 3748184Ssomayeh@cs.wisc.edu 3757550SBrad.Beckmann@amd.com // 3767550SBrad.Beckmann@amd.com // For Alpha, properly handle LL, SC, and write requests with respect to 3777550SBrad.Beckmann@amd.com // locked cache blocks. 3787550SBrad.Beckmann@amd.com // 3798171Stushar@csail.mit.edu // Not valid for Network_test protocl 3808171Stushar@csail.mit.edu // 3818171Stushar@csail.mit.edu bool success = true; 38211321Ssteve.reinhardt@amd.com if (!m_usingNetworkTester) 3838171Stushar@csail.mit.edu success = handleLlsc(address, request); 3847550SBrad.Beckmann@amd.com 3858615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Locked_RMW_Read) { 3867039Snate@binkert.org m_controller->blockOnQueue(address, m_mandatory_q_ptr); 3878615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { 3887039Snate@binkert.org m_controller->unblock(address); 3897039Snate@binkert.org } 3906863Sdrh5@cs.wisc.edu 3919773Snilay@cs.wisc.edu hitCallback(request, data, success, mach, externalHit, 3927565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 3936145Snate@binkert.org} 3946145Snate@binkert.org 3957039Snate@binkert.orgvoid 39611025Snilay@cs.wisc.eduSequencer::readCallback(Addr address, DataBlock& data, 3979773Snilay@cs.wisc.edu bool externalHit, const MachineType mach, 3989507Snilay@cs.wisc.edu Cycles initialRequestTime, 3999507Snilay@cs.wisc.edu Cycles forwardRequestTime, 4009507Snilay@cs.wisc.edu Cycles firstResponseTime) 4017565SBrad.Beckmann@amd.com{ 40211025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 40311025Snilay@cs.wisc.edu assert(m_readRequestTable.count(makeLineAddress(address))); 4046145Snate@binkert.org 4057455Snate@binkert.org RequestTable::iterator i = m_readRequestTable.find(address); 4067455Snate@binkert.org assert(i != m_readRequestTable.end()); 4077455Snate@binkert.org SequencerRequest* request = i->second; 4087455Snate@binkert.org 4097455Snate@binkert.org m_readRequestTable.erase(i); 4107455Snate@binkert.org markRemoved(); 4116145Snate@binkert.org 4128615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_LD) || 4138615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_IFETCH)); 4146285Snate@binkert.org 4159773Snilay@cs.wisc.edu hitCallback(request, data, true, mach, externalHit, 4167565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 4176145Snate@binkert.org} 4186145Snate@binkert.org 4197039Snate@binkert.orgvoid 4209773Snilay@cs.wisc.eduSequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, 4219773Snilay@cs.wisc.edu bool llscSuccess, 4229773Snilay@cs.wisc.edu const MachineType mach, const bool externalHit, 4239773Snilay@cs.wisc.edu const Cycles initialRequestTime, 4249773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 4259773Snilay@cs.wisc.edu const Cycles firstResponseTime) 4267039Snate@binkert.org{ 42711087Snilay@cs.wisc.edu warn_once("Replacement policy updates recently became the responsibility " 42811087Snilay@cs.wisc.edu "of SLICC state machines. Make sure to setMRU() near callbacks " 42911087Snilay@cs.wisc.edu "in .sm files!"); 43011087Snilay@cs.wisc.edu 4318615Snilay@cs.wisc.edu PacketPtr pkt = srequest->pkt; 43211025Snilay@cs.wisc.edu Addr request_address(pkt->getAddr()); 4338615Snilay@cs.wisc.edu RubyRequestType type = srequest->m_type; 4349507Snilay@cs.wisc.edu Cycles issued_time = srequest->issue_time; 4356145Snate@binkert.org 4369465Snilay@cs.wisc.edu assert(curCycle() >= issued_time); 4379773Snilay@cs.wisc.edu Cycles total_latency = curCycle() - issued_time; 4386145Snate@binkert.org 4399773Snilay@cs.wisc.edu // Profile the latency for all demand accesses. 4409773Snilay@cs.wisc.edu recordMissLatency(total_latency, type, mach, externalHit, issued_time, 4419773Snilay@cs.wisc.edu initialRequestTime, forwardRequestTime, 4429773Snilay@cs.wisc.edu firstResponseTime, curCycle()); 4436285Snate@binkert.org 44411025Snilay@cs.wisc.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n", 4459773Snilay@cs.wisc.edu curTick(), m_version, "Seq", 4469773Snilay@cs.wisc.edu llscSuccess ? "Done" : "SC_Failed", "", "", 44711118Snilay@cs.wisc.edu printAddress(request_address), total_latency); 4486285Snate@binkert.org 44910562Sandreas.hansson@arm.com // update the data unless it is a non-data-carrying flush 45010837Sjthestness@gmail.com if (RubySystem::getWarmupEnabled()) { 45110563Sandreas.hansson@arm.com data.setData(pkt->getConstPtr<uint8_t>(), 45211025Snilay@cs.wisc.edu getOffset(request_address), pkt->getSize()); 45310562Sandreas.hansson@arm.com } else if (!pkt->isFlush()) { 4547039Snate@binkert.org if ((type == RubyRequestType_LD) || 4557039Snate@binkert.org (type == RubyRequestType_IFETCH) || 4567039Snate@binkert.org (type == RubyRequestType_RMW_Read) || 4577908Shestness@cs.utexas.edu (type == RubyRequestType_Locked_RMW_Read) || 4587907Shestness@cs.utexas.edu (type == RubyRequestType_Load_Linked)) { 45910562Sandreas.hansson@arm.com memcpy(pkt->getPtr<uint8_t>(), 46011025Snilay@cs.wisc.edu data.getData(getOffset(request_address), pkt->getSize()), 4618615Snilay@cs.wisc.edu pkt->getSize()); 46210954SBrad.Beckmann@amd.com DPRINTF(RubySequencer, "read data %s\n", data); 4637039Snate@binkert.org } else { 46410563Sandreas.hansson@arm.com data.setData(pkt->getConstPtr<uint8_t>(), 46511025Snilay@cs.wisc.edu getOffset(request_address), pkt->getSize()); 46610954SBrad.Beckmann@amd.com DPRINTF(RubySequencer, "set data %s\n", data); 4677039Snate@binkert.org } 4687039Snate@binkert.org } 4697023SBrad.Beckmann@amd.com 4707039Snate@binkert.org // If using the RubyTester, update the RubyTester sender state's 4717039Snate@binkert.org // subBlock with the recieved data. The tester will later access 4727039Snate@binkert.org // this state. 4737039Snate@binkert.org if (m_usingRubyTester) { 47410657Sandreas.hansson@arm.com DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n", 47510657Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 4767039Snate@binkert.org RubyTester::SenderState* testerSenderState = 47710089Sandreas.hansson@arm.com pkt->findNextSenderState<RubyTester::SenderState>(); 47810089Sandreas.hansson@arm.com assert(testerSenderState); 4799542Sandreas.hansson@arm.com testerSenderState->subBlock.mergeFrom(data); 4807039Snate@binkert.org } 4817023SBrad.Beckmann@amd.com 4827039Snate@binkert.org delete srequest; 4838688Snilay@cs.wisc.edu 48410919Sbrandon.potter@amd.com RubySystem *rs = m_ruby_system; 48510837Sjthestness@gmail.com if (RubySystem::getWarmupEnabled()) { 4869632Sjthestness@gmail.com assert(pkt->req); 4879632Sjthestness@gmail.com delete pkt->req; 4888688Snilay@cs.wisc.edu delete pkt; 48910919Sbrandon.potter@amd.com rs->m_cache_recorder->enqueueNextFetchRequest(); 49010837Sjthestness@gmail.com } else if (RubySystem::getCooldownEnabled()) { 4918688Snilay@cs.wisc.edu delete pkt; 49210919Sbrandon.potter@amd.com rs->m_cache_recorder->enqueueNextFlushRequest(); 4938688Snilay@cs.wisc.edu } else { 4948688Snilay@cs.wisc.edu ruby_hit_callback(pkt); 49511266SBrad.Beckmann@amd.com testDrainComplete(); 4968688Snilay@cs.wisc.edu } 4976285Snate@binkert.org} 4986285Snate@binkert.org 4997039Snate@binkert.orgbool 5007039Snate@binkert.orgSequencer::empty() const 5017039Snate@binkert.org{ 5027455Snate@binkert.org return m_writeRequestTable.empty() && m_readRequestTable.empty(); 5036145Snate@binkert.org} 5046145Snate@binkert.org 5057039Snate@binkert.orgRequestStatus 5068615Snilay@cs.wisc.eduSequencer::makeRequest(PacketPtr pkt) 5077039Snate@binkert.org{ 5088615Snilay@cs.wisc.edu if (m_outstanding_count >= m_max_outstanding_requests) { 5098615Snilay@cs.wisc.edu return RequestStatus_BufferFull; 5108615Snilay@cs.wisc.edu } 5118615Snilay@cs.wisc.edu 5128615Snilay@cs.wisc.edu RubyRequestType primary_type = RubyRequestType_NULL; 5138615Snilay@cs.wisc.edu RubyRequestType secondary_type = RubyRequestType_NULL; 5148615Snilay@cs.wisc.edu 5158615Snilay@cs.wisc.edu if (pkt->isLLSC()) { 5168615Snilay@cs.wisc.edu // 5178615Snilay@cs.wisc.edu // Alpha LL/SC instructions need to be handled carefully by the cache 5188615Snilay@cs.wisc.edu // coherence protocol to ensure they follow the proper semantics. In 5198615Snilay@cs.wisc.edu // particular, by identifying the operations as atomic, the protocol 5208615Snilay@cs.wisc.edu // should understand that migratory sharing optimizations should not 5218615Snilay@cs.wisc.edu // be performed (i.e. a load between the LL and SC should not steal 5228615Snilay@cs.wisc.edu // away exclusive permission). 5238615Snilay@cs.wisc.edu // 5248615Snilay@cs.wisc.edu if (pkt->isWrite()) { 5258615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing SC\n"); 5268615Snilay@cs.wisc.edu primary_type = RubyRequestType_Store_Conditional; 5278615Snilay@cs.wisc.edu } else { 5288615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing LL\n"); 5298615Snilay@cs.wisc.edu assert(pkt->isRead()); 5308615Snilay@cs.wisc.edu primary_type = RubyRequestType_Load_Linked; 5318615Snilay@cs.wisc.edu } 5328615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ATOMIC; 53310760Ssteve.reinhardt@amd.com } else if (pkt->req->isLockedRMW()) { 5348615Snilay@cs.wisc.edu // 5358615Snilay@cs.wisc.edu // x86 locked instructions are translated to store cache coherence 5368615Snilay@cs.wisc.edu // requests because these requests should always be treated as read 5378615Snilay@cs.wisc.edu // exclusive operations and should leverage any migratory sharing 5388615Snilay@cs.wisc.edu // optimization built into the protocol. 5398615Snilay@cs.wisc.edu // 5408615Snilay@cs.wisc.edu if (pkt->isWrite()) { 5418615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); 5428615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Write; 5438615Snilay@cs.wisc.edu } else { 5448615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); 5458615Snilay@cs.wisc.edu assert(pkt->isRead()); 5468615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Read; 5478615Snilay@cs.wisc.edu } 5488615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 5498615Snilay@cs.wisc.edu } else { 5508615Snilay@cs.wisc.edu if (pkt->isRead()) { 5518615Snilay@cs.wisc.edu if (pkt->req->isInstFetch()) { 5528615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_IFETCH; 5538615Snilay@cs.wisc.edu } else { 5548615Snilay@cs.wisc.edu bool storeCheck = false; 55510467Sandreas.hansson@arm.com // only X86 need the store check 55610467Sandreas.hansson@arm.com if (system->getArch() == Arch::X86ISA) { 55710467Sandreas.hansson@arm.com uint32_t flags = pkt->req->getFlags(); 55810467Sandreas.hansson@arm.com storeCheck = flags & 55910467Sandreas.hansson@arm.com (X86ISA::StoreCheck << X86ISA::FlagShift); 56010467Sandreas.hansson@arm.com } 5618615Snilay@cs.wisc.edu if (storeCheck) { 5628615Snilay@cs.wisc.edu primary_type = RubyRequestType_RMW_Read; 5638615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 5648615Snilay@cs.wisc.edu } else { 5658615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_LD; 5668615Snilay@cs.wisc.edu } 5678615Snilay@cs.wisc.edu } 5688615Snilay@cs.wisc.edu } else if (pkt->isWrite()) { 5698615Snilay@cs.wisc.edu // 5708615Snilay@cs.wisc.edu // Note: M5 packets do not differentiate ST from RMW_Write 5718615Snilay@cs.wisc.edu // 5728615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_ST; 5738615Snilay@cs.wisc.edu } else if (pkt->isFlush()) { 5748615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_FLUSH; 5758615Snilay@cs.wisc.edu } else { 5768615Snilay@cs.wisc.edu panic("Unsupported ruby packet type\n"); 5778615Snilay@cs.wisc.edu } 5788615Snilay@cs.wisc.edu } 5798615Snilay@cs.wisc.edu 5808615Snilay@cs.wisc.edu RequestStatus status = insertRequest(pkt, primary_type); 5817039Snate@binkert.org if (status != RequestStatus_Ready) 5827039Snate@binkert.org return status; 5836349Spdudnik@gmail.com 5848615Snilay@cs.wisc.edu issueRequest(pkt, secondary_type); 5856145Snate@binkert.org 5867039Snate@binkert.org // TODO: issue hardware prefetches here 5877039Snate@binkert.org return RequestStatus_Issued; 5886145Snate@binkert.org} 5896145Snate@binkert.org 5907039Snate@binkert.orgvoid 5918615Snilay@cs.wisc.eduSequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) 5927039Snate@binkert.org{ 5939216Sandreas.hansson@arm.com assert(pkt != NULL); 59411005Sandreas.sandberg@arm.com ContextID proc_id = pkt->req->hasContextId() ? 59511005Sandreas.sandberg@arm.com pkt->req->contextId() : InvalidContextID; 5966285Snate@binkert.org 59711308Santhony.gutierrez@amd.com ContextID core_id = coreId(); 59811308Santhony.gutierrez@amd.com 5998615Snilay@cs.wisc.edu // If valid, copy the pc to the ruby request 6008615Snilay@cs.wisc.edu Addr pc = 0; 6018615Snilay@cs.wisc.edu if (pkt->req->hasPC()) { 6028615Snilay@cs.wisc.edu pc = pkt->req->getPC(); 6037039Snate@binkert.org } 6046285Snate@binkert.org 60510562Sandreas.hansson@arm.com // check if the packet has data as for example prefetch and flush 60610562Sandreas.hansson@arm.com // requests do not 60710472Sandreas.hansson@arm.com std::shared_ptr<RubyRequest> msg = 60810472Sandreas.hansson@arm.com std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(), 60910562Sandreas.hansson@arm.com pkt->isFlush() ? 61010562Sandreas.hansson@arm.com nullptr : pkt->getPtr<uint8_t>(), 61110472Sandreas.hansson@arm.com pkt->getSize(), pc, secondary_type, 61210472Sandreas.hansson@arm.com RubyAccessMode_Supervisor, pkt, 61311308Santhony.gutierrez@amd.com PrefetchBit_No, proc_id, core_id); 6146285Snate@binkert.org 61511025Snilay@cs.wisc.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n", 6168266Sksewell@umich.edu curTick(), m_version, "Seq", "Begin", "", "", 61711118Snilay@cs.wisc.edu printAddress(msg->getPhysicalAddress()), 6188615Snilay@cs.wisc.edu RubyRequestType_to_string(secondary_type)); 6196285Snate@binkert.org 62011019Sjthestness@gmail.com // The Sequencer currently assesses instruction and data cache hit latency 62111019Sjthestness@gmail.com // for the top-level caches at the beginning of a memory access. 62211019Sjthestness@gmail.com // TODO: Eventually, this latency should be moved to represent the actual 62311019Sjthestness@gmail.com // cache access latency portion of the memory access. This will require 62411019Sjthestness@gmail.com // changing cache controller protocol files to assess the latency on the 62511019Sjthestness@gmail.com // access response path. 62611019Sjthestness@gmail.com Cycles latency(0); // Initialize to zero to catch misconfigured latency 6278615Snilay@cs.wisc.edu if (secondary_type == RubyRequestType_IFETCH) 62811019Sjthestness@gmail.com latency = m_inst_cache_hit_latency; 6297039Snate@binkert.org else 63011019Sjthestness@gmail.com latency = m_data_cache_hit_latency; 6316285Snate@binkert.org 6327039Snate@binkert.org // Send the message to the cache controller 6337039Snate@binkert.org assert(latency > 0); 6346145Snate@binkert.org 6357039Snate@binkert.org assert(m_mandatory_q_ptr != NULL); 63611111Snilay@cs.wisc.edu m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(latency)); 6376145Snate@binkert.org} 6386145Snate@binkert.org 6397455Snate@binkert.orgtemplate <class KEY, class VALUE> 6407455Snate@binkert.orgstd::ostream & 64111168Sandreas.hansson@arm.comoperator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map) 6427455Snate@binkert.org{ 64311168Sandreas.hansson@arm.com auto i = map.begin(); 64411168Sandreas.hansson@arm.com auto end = map.end(); 6457455Snate@binkert.org 6467455Snate@binkert.org out << "["; 6477455Snate@binkert.org for (; i != end; ++i) 6487455Snate@binkert.org out << " " << i->first << "=" << i->second; 6497455Snate@binkert.org out << " ]"; 6507455Snate@binkert.org 6517455Snate@binkert.org return out; 6527455Snate@binkert.org} 6537455Snate@binkert.org 6547039Snate@binkert.orgvoid 6557039Snate@binkert.orgSequencer::print(ostream& out) const 6567039Snate@binkert.org{ 6577039Snate@binkert.org out << "[Sequencer: " << m_version 6587039Snate@binkert.org << ", outstanding requests: " << m_outstanding_count 6597039Snate@binkert.org << ", read request table: " << m_readRequestTable 6607039Snate@binkert.org << ", write request table: " << m_writeRequestTable 6617039Snate@binkert.org << "]"; 6627039Snate@binkert.org} 6637039Snate@binkert.org 6647039Snate@binkert.org// this can be called from setState whenever coherence permissions are 6657039Snate@binkert.org// upgraded when invoked, coherence violations will be checked for the 6667039Snate@binkert.org// given block 6677039Snate@binkert.orgvoid 66811025Snilay@cs.wisc.eduSequencer::checkCoherence(Addr addr) 6697039Snate@binkert.org{ 6706145Snate@binkert.org#ifdef CHECK_COHERENCE 67110919Sbrandon.potter@amd.com m_ruby_system->checkGlobalCoherenceInvariant(addr); 6726145Snate@binkert.org#endif 6736145Snate@binkert.org} 6748717Snilay@cs.wisc.edu 6758717Snilay@cs.wisc.eduvoid 6769104Shestness@cs.utexas.eduSequencer::recordRequestType(SequencerRequestType requestType) { 6779104Shestness@cs.utexas.edu DPRINTF(RubyStats, "Recorded statistic: %s\n", 6789104Shestness@cs.utexas.edu SequencerRequestType_to_string(requestType)); 6799104Shestness@cs.utexas.edu} 6809104Shestness@cs.utexas.edu 6819104Shestness@cs.utexas.edu 6829104Shestness@cs.utexas.eduvoid 68311025Snilay@cs.wisc.eduSequencer::evictionCallback(Addr address) 6848717Snilay@cs.wisc.edu{ 6858717Snilay@cs.wisc.edu ruby_eviction_callback(address); 6868717Snilay@cs.wisc.edu} 68710012Snilay@cs.wisc.edu 68810012Snilay@cs.wisc.eduvoid 68910012Snilay@cs.wisc.eduSequencer::regStats() 69010012Snilay@cs.wisc.edu{ 69110012Snilay@cs.wisc.edu m_store_waiting_on_load 69210012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_load") 69310012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending load") 69410012Snilay@cs.wisc.edu .flags(Stats::nozero); 69510012Snilay@cs.wisc.edu m_store_waiting_on_store 69610012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_store") 69710012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending store") 69810012Snilay@cs.wisc.edu .flags(Stats::nozero); 69910012Snilay@cs.wisc.edu m_load_waiting_on_load 70010012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_load") 70110012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending load") 70210012Snilay@cs.wisc.edu .flags(Stats::nozero); 70310012Snilay@cs.wisc.edu m_load_waiting_on_store 70410012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_store") 70510012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending store") 70610012Snilay@cs.wisc.edu .flags(Stats::nozero); 70710012Snilay@cs.wisc.edu 70810012Snilay@cs.wisc.edu // These statistical variables are not for display. 70910012Snilay@cs.wisc.edu // The profiler will collate these across different 71010012Snilay@cs.wisc.edu // sequencers and display those collated statistics. 71110012Snilay@cs.wisc.edu m_outstandReqHist.init(10); 71210012Snilay@cs.wisc.edu m_latencyHist.init(10); 71310012Snilay@cs.wisc.edu m_hitLatencyHist.init(10); 71410012Snilay@cs.wisc.edu m_missLatencyHist.init(10); 71510012Snilay@cs.wisc.edu 71610012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 71710012Snilay@cs.wisc.edu m_typeLatencyHist.push_back(new Stats::Histogram()); 71810012Snilay@cs.wisc.edu m_typeLatencyHist[i]->init(10); 71910012Snilay@cs.wisc.edu 72010012Snilay@cs.wisc.edu m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 72110012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->init(10); 72210012Snilay@cs.wisc.edu 72310012Snilay@cs.wisc.edu m_missTypeLatencyHist.push_back(new Stats::Histogram()); 72410012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->init(10); 72510012Snilay@cs.wisc.edu } 72610012Snilay@cs.wisc.edu 72710012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 72810012Snilay@cs.wisc.edu m_hitMachLatencyHist.push_back(new Stats::Histogram()); 72910012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->init(10); 73010012Snilay@cs.wisc.edu 73110012Snilay@cs.wisc.edu m_missMachLatencyHist.push_back(new Stats::Histogram()); 73210012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->init(10); 73310012Snilay@cs.wisc.edu 73410012Snilay@cs.wisc.edu m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 73510012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->init(10); 73610012Snilay@cs.wisc.edu 73710012Snilay@cs.wisc.edu m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 73810012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->init(10); 73910012Snilay@cs.wisc.edu 74010012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 74110012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->init(10); 74210012Snilay@cs.wisc.edu 74310012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 74410012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->init(10); 74510012Snilay@cs.wisc.edu } 74610012Snilay@cs.wisc.edu 74710012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 74810012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 74910012Snilay@cs.wisc.edu m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 75010012Snilay@cs.wisc.edu 75110012Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 75210012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 75310012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->init(10); 75410012Snilay@cs.wisc.edu 75510012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 75610012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->init(10); 75710012Snilay@cs.wisc.edu } 75810012Snilay@cs.wisc.edu } 75910012Snilay@cs.wisc.edu} 760