Sequencer.cc revision 10467
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org */ 286145Snate@binkert.org 2910467Sandreas.hansson@arm.com#include "arch/x86/ldstflags.hh" 308229Snate@binkert.org#include "base/misc.hh" 317056Snate@binkert.org#include "base/str.hh" 327632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 338232Snate@binkert.org#include "debug/MemoryAccess.hh" 348232Snate@binkert.org#include "debug/ProtocolTrace.hh" 358615Snilay@cs.wisc.edu#include "debug/RubySequencer.hh" 369104Shestness@cs.utexas.edu#include "debug/RubyStats.hh" 378615Snilay@cs.wisc.edu#include "mem/protocol/PrefetchBit.hh" 388615Snilay@cs.wisc.edu#include "mem/protocol/RubyAccessMode.hh" 397039Snate@binkert.org#include "mem/ruby/common/Global.hh" 407039Snate@binkert.org#include "mem/ruby/profiler/Profiler.hh" 418229Snate@binkert.org#include "mem/ruby/slicc_interface/RubyRequest.hh" 426154Snate@binkert.org#include "mem/ruby/system/Sequencer.hh" 436154Snate@binkert.org#include "mem/ruby/system/System.hh" 447550SBrad.Beckmann@amd.com#include "mem/packet.hh" 4510467Sandreas.hansson@arm.com#include "sim/system.hh" 466876Ssteve.reinhardt@amd.com 477055Snate@binkert.orgusing namespace std; 487055Snate@binkert.org 496876Ssteve.reinhardt@amd.comSequencer * 506876Ssteve.reinhardt@amd.comRubySequencerParams::create() 516285Snate@binkert.org{ 526876Ssteve.reinhardt@amd.com return new Sequencer(this); 536285Snate@binkert.org} 547039Snate@binkert.org 556876Ssteve.reinhardt@amd.comSequencer::Sequencer(const Params *p) 5610012Snilay@cs.wisc.edu : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this) 576876Ssteve.reinhardt@amd.com{ 586876Ssteve.reinhardt@amd.com m_outstanding_count = 0; 596285Snate@binkert.org 606876Ssteve.reinhardt@amd.com m_instCache_ptr = p->icache; 616876Ssteve.reinhardt@amd.com m_dataCache_ptr = p->dcache; 626876Ssteve.reinhardt@amd.com m_max_outstanding_requests = p->max_outstanding_requests; 636876Ssteve.reinhardt@amd.com m_deadlock_threshold = p->deadlock_threshold; 646899SBrad.Beckmann@amd.com 656876Ssteve.reinhardt@amd.com assert(m_max_outstanding_requests > 0); 666876Ssteve.reinhardt@amd.com assert(m_deadlock_threshold > 0); 676876Ssteve.reinhardt@amd.com assert(m_instCache_ptr != NULL); 686876Ssteve.reinhardt@amd.com assert(m_dataCache_ptr != NULL); 698171Stushar@csail.mit.edu 708171Stushar@csail.mit.edu m_usingNetworkTester = p->using_network_tester; 716145Snate@binkert.org} 726145Snate@binkert.org 737039Snate@binkert.orgSequencer::~Sequencer() 747039Snate@binkert.org{ 756145Snate@binkert.org} 766145Snate@binkert.org 777039Snate@binkert.orgvoid 787039Snate@binkert.orgSequencer::wakeup() 797039Snate@binkert.org{ 809342SAndreas.Sandberg@arm.com assert(getDrainState() != Drainable::Draining); 819245Shestness@cs.wisc.edu 827039Snate@binkert.org // Check for deadlock of any of the requests 839501Snilay@cs.wisc.edu Cycles current_time = curCycle(); 846145Snate@binkert.org 857039Snate@binkert.org // Check across all outstanding requests 867039Snate@binkert.org int total_outstanding = 0; 876285Snate@binkert.org 887455Snate@binkert.org RequestTable::iterator read = m_readRequestTable.begin(); 897455Snate@binkert.org RequestTable::iterator read_end = m_readRequestTable.end(); 907455Snate@binkert.org for (; read != read_end; ++read) { 917455Snate@binkert.org SequencerRequest* request = read->second; 927455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 937455Snate@binkert.org continue; 947455Snate@binkert.org 957805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 967921SBrad.Beckmann@amd.com "version: %d request.paddr: 0x%x m_readRequestTable: %d " 977805Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 988615Snilay@cs.wisc.edu Address(request->pkt->getAddr()), m_readRequestTable.size(), 999467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1009467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1016145Snate@binkert.org } 1026145Snate@binkert.org 1037455Snate@binkert.org RequestTable::iterator write = m_writeRequestTable.begin(); 1047455Snate@binkert.org RequestTable::iterator write_end = m_writeRequestTable.end(); 1057455Snate@binkert.org for (; write != write_end; ++write) { 1067455Snate@binkert.org SequencerRequest* request = write->second; 1077455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 1087455Snate@binkert.org continue; 1097455Snate@binkert.org 1107805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 1117921SBrad.Beckmann@amd.com "version: %d request.paddr: 0x%x m_writeRequestTable: %d " 1127805Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 1138615Snilay@cs.wisc.edu Address(request->pkt->getAddr()), m_writeRequestTable.size(), 1149467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1159467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1166145Snate@binkert.org } 1176285Snate@binkert.org 1187039Snate@binkert.org total_outstanding += m_writeRequestTable.size(); 1197039Snate@binkert.org total_outstanding += m_readRequestTable.size(); 1206145Snate@binkert.org 1217039Snate@binkert.org assert(m_outstanding_count == total_outstanding); 1227039Snate@binkert.org 1237039Snate@binkert.org if (m_outstanding_count > 0) { 1247039Snate@binkert.org // If there are still outstanding requests, keep checking 1259465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 1267039Snate@binkert.org } 1276145Snate@binkert.org} 1286145Snate@binkert.org 12910012Snilay@cs.wisc.eduvoid Sequencer::resetStats() 1309598Snilay@cs.wisc.edu{ 13110012Snilay@cs.wisc.edu m_latencyHist.reset(); 13210012Snilay@cs.wisc.edu m_hitLatencyHist.reset(); 13310012Snilay@cs.wisc.edu m_missLatencyHist.reset(); 1349773Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 13510012Snilay@cs.wisc.edu m_typeLatencyHist[i]->reset(); 13610012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->reset(); 13710012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->reset(); 1389773Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 13910012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->reset(); 14010012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->reset(); 1419773Snilay@cs.wisc.edu } 1429773Snilay@cs.wisc.edu } 1439773Snilay@cs.wisc.edu 14410012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 14510012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->reset(); 14610012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->reset(); 1479773Snilay@cs.wisc.edu 14810012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->reset(); 14910012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->reset(); 15010012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->reset(); 15110012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->reset(); 1529773Snilay@cs.wisc.edu 1539773Snilay@cs.wisc.edu m_IncompleteTimes[i] = 0; 1549773Snilay@cs.wisc.edu } 1559598Snilay@cs.wisc.edu} 1569598Snilay@cs.wisc.edu 1577039Snate@binkert.orgvoid 1587039Snate@binkert.orgSequencer::printProgress(ostream& out) const 1597039Snate@binkert.org{ 1607039Snate@binkert.org#if 0 1617039Snate@binkert.org int total_demand = 0; 1627039Snate@binkert.org out << "Sequencer Stats Version " << m_version << endl; 1639171Snilay@cs.wisc.edu out << "Current time = " << g_system_ptr->getTime() << endl; 1647039Snate@binkert.org out << "---------------" << endl; 1657039Snate@binkert.org out << "outstanding requests" << endl; 1666145Snate@binkert.org 1677455Snate@binkert.org out << "proc " << m_Read 1687455Snate@binkert.org << " version Requests = " << m_readRequestTable.size() << endl; 1696145Snate@binkert.org 1707039Snate@binkert.org // print the request table 1717455Snate@binkert.org RequestTable::iterator read = m_readRequestTable.begin(); 1727455Snate@binkert.org RequestTable::iterator read_end = m_readRequestTable.end(); 1737455Snate@binkert.org for (; read != read_end; ++read) { 1747455Snate@binkert.org SequencerRequest* request = read->second; 1757039Snate@binkert.org out << "\tRequest[ " << i << " ] = " << request->type 1767039Snate@binkert.org << " Address " << rkeys[i] 1777039Snate@binkert.org << " Posted " << request->issue_time 1787039Snate@binkert.org << " PF " << PrefetchBit_No << endl; 1796145Snate@binkert.org total_demand++; 1807039Snate@binkert.org } 1816145Snate@binkert.org 1827455Snate@binkert.org out << "proc " << m_version 1837455Snate@binkert.org << " Write Requests = " << m_writeRequestTable.size << endl; 1846285Snate@binkert.org 1857039Snate@binkert.org // print the request table 1867455Snate@binkert.org RequestTable::iterator write = m_writeRequestTable.begin(); 1877455Snate@binkert.org RequestTable::iterator write_end = m_writeRequestTable.end(); 1887455Snate@binkert.org for (; write != write_end; ++write) { 1897455Snate@binkert.org SequencerRequest* request = write->second; 1907039Snate@binkert.org out << "\tRequest[ " << i << " ] = " << request.getType() 1917039Snate@binkert.org << " Address " << wkeys[i] 1927039Snate@binkert.org << " Posted " << request.getTime() 1937039Snate@binkert.org << " PF " << request.getPrefetch() << endl; 1947039Snate@binkert.org if (request.getPrefetch() == PrefetchBit_No) { 1957039Snate@binkert.org total_demand++; 1967039Snate@binkert.org } 1977039Snate@binkert.org } 1987039Snate@binkert.org 1997039Snate@binkert.org out << endl; 2007039Snate@binkert.org 2017039Snate@binkert.org out << "Total Number Outstanding: " << m_outstanding_count << endl 2027039Snate@binkert.org << "Total Number Demand : " << total_demand << endl 2037039Snate@binkert.org << "Total Number Prefetches : " << m_outstanding_count - total_demand 2047039Snate@binkert.org << endl << endl << endl; 2057039Snate@binkert.org#endif 2066145Snate@binkert.org} 2076145Snate@binkert.org 2086145Snate@binkert.org// Insert the request on the correct request table. Return true if 2096145Snate@binkert.org// the entry was already present. 2108615Snilay@cs.wisc.eduRequestStatus 2118615Snilay@cs.wisc.eduSequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 2127039Snate@binkert.org{ 2138641Snate@binkert.org assert(m_outstanding_count == 2148641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 2156145Snate@binkert.org 2167039Snate@binkert.org // See if we should schedule a deadlock check 2179342SAndreas.Sandberg@arm.com if (!deadlockCheckEvent.scheduled() && 2189342SAndreas.Sandberg@arm.com getDrainState() != Drainable::Draining) { 2199465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 2207039Snate@binkert.org } 2216145Snate@binkert.org 2228615Snilay@cs.wisc.edu Address line_addr(pkt->getAddr()); 2237039Snate@binkert.org line_addr.makeLineAddress(); 2249224Sandreas.hansson@arm.com // Create a default entry, mapping the address to NULL, the cast is 2259224Sandreas.hansson@arm.com // there to make gcc 4.4 happy 2269224Sandreas.hansson@arm.com RequestTable::value_type default_entry(line_addr, 2279224Sandreas.hansson@arm.com (SequencerRequest*) NULL); 2289224Sandreas.hansson@arm.com 2298615Snilay@cs.wisc.edu if ((request_type == RubyRequestType_ST) || 2308615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Read) || 2318615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Write) || 2328615Snilay@cs.wisc.edu (request_type == RubyRequestType_Load_Linked) || 2338615Snilay@cs.wisc.edu (request_type == RubyRequestType_Store_Conditional) || 2348615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Read) || 2358615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Write) || 2368615Snilay@cs.wisc.edu (request_type == RubyRequestType_FLUSH)) { 2378615Snilay@cs.wisc.edu 2388615Snilay@cs.wisc.edu // Check if there is any outstanding read request for the same 2398615Snilay@cs.wisc.edu // cache line. 2408615Snilay@cs.wisc.edu if (m_readRequestTable.count(line_addr) > 0) { 24110012Snilay@cs.wisc.edu m_store_waiting_on_load++; 2428615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2438615Snilay@cs.wisc.edu } 2448615Snilay@cs.wisc.edu 2457455Snate@binkert.org pair<RequestTable::iterator, bool> r = 2469224Sandreas.hansson@arm.com m_writeRequestTable.insert(default_entry); 2478615Snilay@cs.wisc.edu if (r.second) { 2488615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2499465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2508615Snilay@cs.wisc.edu m_outstanding_count++; 2518615Snilay@cs.wisc.edu } else { 2528615Snilay@cs.wisc.edu // There is an outstanding write request for the cache line 25310012Snilay@cs.wisc.edu m_store_waiting_on_store++; 2548615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2558615Snilay@cs.wisc.edu } 2568615Snilay@cs.wisc.edu } else { 2578615Snilay@cs.wisc.edu // Check if there is any outstanding write request for the same 2588615Snilay@cs.wisc.edu // cache line. 2598615Snilay@cs.wisc.edu if (m_writeRequestTable.count(line_addr) > 0) { 26010012Snilay@cs.wisc.edu m_load_waiting_on_store++; 2618615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2628615Snilay@cs.wisc.edu } 2637039Snate@binkert.org 2647455Snate@binkert.org pair<RequestTable::iterator, bool> r = 2659224Sandreas.hansson@arm.com m_readRequestTable.insert(default_entry); 2667039Snate@binkert.org 2678615Snilay@cs.wisc.edu if (r.second) { 2688615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2699465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2708615Snilay@cs.wisc.edu m_outstanding_count++; 2718615Snilay@cs.wisc.edu } else { 2728615Snilay@cs.wisc.edu // There is an outstanding read request for the cache line 27310012Snilay@cs.wisc.edu m_load_waiting_on_load++; 2748615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2757039Snate@binkert.org } 2766145Snate@binkert.org } 2776145Snate@binkert.org 27810012Snilay@cs.wisc.edu m_outstandReqHist.sample(m_outstanding_count); 2798641Snate@binkert.org assert(m_outstanding_count == 2808641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 2816145Snate@binkert.org 2828615Snilay@cs.wisc.edu return RequestStatus_Ready; 2836145Snate@binkert.org} 2846145Snate@binkert.org 2857039Snate@binkert.orgvoid 2867455Snate@binkert.orgSequencer::markRemoved() 2877455Snate@binkert.org{ 2887455Snate@binkert.org m_outstanding_count--; 2897455Snate@binkert.org assert(m_outstanding_count == 2907455Snate@binkert.org m_writeRequestTable.size() + m_readRequestTable.size()); 2917455Snate@binkert.org} 2927455Snate@binkert.org 2937455Snate@binkert.orgvoid 2947039Snate@binkert.orgSequencer::removeRequest(SequencerRequest* srequest) 2957039Snate@binkert.org{ 2967039Snate@binkert.org assert(m_outstanding_count == 2977039Snate@binkert.org m_writeRequestTable.size() + m_readRequestTable.size()); 2986145Snate@binkert.org 2998615Snilay@cs.wisc.edu Address line_addr(srequest->pkt->getAddr()); 3007039Snate@binkert.org line_addr.makeLineAddress(); 3018615Snilay@cs.wisc.edu if ((srequest->m_type == RubyRequestType_ST) || 3028615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_RMW_Read) || 3038615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_RMW_Write) || 3048615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Load_Linked) || 3058615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Store_Conditional) || 3068615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Locked_RMW_Read) || 3078615Snilay@cs.wisc.edu (srequest->m_type == RubyRequestType_Locked_RMW_Write)) { 3087455Snate@binkert.org m_writeRequestTable.erase(line_addr); 3097039Snate@binkert.org } else { 3107455Snate@binkert.org m_readRequestTable.erase(line_addr); 3117039Snate@binkert.org } 3126285Snate@binkert.org 3137455Snate@binkert.org markRemoved(); 3146145Snate@binkert.org} 3156145Snate@binkert.org 3169563Sgope@wisc.eduvoid 3179563Sgope@wisc.eduSequencer::invalidateSC(const Address& address) 3189563Sgope@wisc.edu{ 3199563Sgope@wisc.edu RequestTable::iterator i = m_writeRequestTable.find(address); 3209563Sgope@wisc.edu if (i != m_writeRequestTable.end()) { 3219563Sgope@wisc.edu SequencerRequest* request = i->second; 3229563Sgope@wisc.edu // The controller has lost the coherence permissions, hence the lock 3239563Sgope@wisc.edu // on the cache line maintained by the cache should be cleared. 3249563Sgope@wisc.edu if (request->m_type == RubyRequestType_Store_Conditional) { 3259563Sgope@wisc.edu m_dataCache_ptr->clearLocked(address); 3269563Sgope@wisc.edu } 3279563Sgope@wisc.edu } 3289563Sgope@wisc.edu} 3299563Sgope@wisc.edu 3307560SBrad.Beckmann@amd.combool 3317560SBrad.Beckmann@amd.comSequencer::handleLlsc(const Address& address, SequencerRequest* request) 3327550SBrad.Beckmann@amd.com{ 3337560SBrad.Beckmann@amd.com // 3347560SBrad.Beckmann@amd.com // The success flag indicates whether the LLSC operation was successful. 3357560SBrad.Beckmann@amd.com // LL ops will always succeed, but SC may fail if the cache line is no 3367560SBrad.Beckmann@amd.com // longer locked. 3377560SBrad.Beckmann@amd.com // 3387560SBrad.Beckmann@amd.com bool success = true; 3398615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Store_Conditional) { 3407550SBrad.Beckmann@amd.com if (!m_dataCache_ptr->isLocked(address, m_version)) { 3417550SBrad.Beckmann@amd.com // 3427550SBrad.Beckmann@amd.com // For failed SC requests, indicate the failure to the cpu by 3437550SBrad.Beckmann@amd.com // setting the extra data to zero. 3447550SBrad.Beckmann@amd.com // 3458615Snilay@cs.wisc.edu request->pkt->req->setExtraData(0); 3467560SBrad.Beckmann@amd.com success = false; 3477550SBrad.Beckmann@amd.com } else { 3487550SBrad.Beckmann@amd.com // 3497550SBrad.Beckmann@amd.com // For successful SC requests, indicate the success to the cpu by 3507550SBrad.Beckmann@amd.com // setting the extra data to one. 3517550SBrad.Beckmann@amd.com // 3528615Snilay@cs.wisc.edu request->pkt->req->setExtraData(1); 3537550SBrad.Beckmann@amd.com } 3547560SBrad.Beckmann@amd.com // 3557560SBrad.Beckmann@amd.com // Independent of success, all SC operations must clear the lock 3567560SBrad.Beckmann@amd.com // 3577550SBrad.Beckmann@amd.com m_dataCache_ptr->clearLocked(address); 3588615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Load_Linked) { 3597550SBrad.Beckmann@amd.com // 3607550SBrad.Beckmann@amd.com // Note: To fully follow Alpha LLSC semantics, should the LL clear any 3617550SBrad.Beckmann@amd.com // previously locked cache lines? 3627550SBrad.Beckmann@amd.com // 3637550SBrad.Beckmann@amd.com m_dataCache_ptr->setLocked(address, m_version); 3648615Snilay@cs.wisc.edu } else if ((m_dataCache_ptr->isTagPresent(address)) && 3658615Snilay@cs.wisc.edu (m_dataCache_ptr->isLocked(address, m_version))) { 3667550SBrad.Beckmann@amd.com // 3677550SBrad.Beckmann@amd.com // Normal writes should clear the locked address 3687550SBrad.Beckmann@amd.com // 3697550SBrad.Beckmann@amd.com m_dataCache_ptr->clearLocked(address); 3707550SBrad.Beckmann@amd.com } 3717560SBrad.Beckmann@amd.com return success; 3727550SBrad.Beckmann@amd.com} 3737550SBrad.Beckmann@amd.com 3747550SBrad.Beckmann@amd.comvoid 3759773Snilay@cs.wisc.eduSequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 3769773Snilay@cs.wisc.edu const MachineType respondingMach, 3779773Snilay@cs.wisc.edu bool isExternalHit, Cycles issuedTime, 3789773Snilay@cs.wisc.edu Cycles initialRequestTime, 3799773Snilay@cs.wisc.edu Cycles forwardRequestTime, 3809773Snilay@cs.wisc.edu Cycles firstResponseTime, Cycles completionTime) 3817039Snate@binkert.org{ 38210012Snilay@cs.wisc.edu m_latencyHist.sample(cycles); 38310012Snilay@cs.wisc.edu m_typeLatencyHist[type]->sample(cycles); 3849773Snilay@cs.wisc.edu 3859773Snilay@cs.wisc.edu if (isExternalHit) { 38610012Snilay@cs.wisc.edu m_missLatencyHist.sample(cycles); 38710012Snilay@cs.wisc.edu m_missTypeLatencyHist[type]->sample(cycles); 3889773Snilay@cs.wisc.edu 3899773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 39010012Snilay@cs.wisc.edu m_missMachLatencyHist[respondingMach]->sample(cycles); 39110012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles); 3929773Snilay@cs.wisc.edu 3939773Snilay@cs.wisc.edu if ((issuedTime <= initialRequestTime) && 3949773Snilay@cs.wisc.edu (initialRequestTime <= forwardRequestTime) && 3959773Snilay@cs.wisc.edu (forwardRequestTime <= firstResponseTime) && 3969773Snilay@cs.wisc.edu (firstResponseTime <= completionTime)) { 3979773Snilay@cs.wisc.edu 39810012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[respondingMach]->sample( 3999773Snilay@cs.wisc.edu initialRequestTime - issuedTime); 40010012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[respondingMach]->sample( 4019773Snilay@cs.wisc.edu forwardRequestTime - initialRequestTime); 40210012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[respondingMach]->sample( 4039773Snilay@cs.wisc.edu firstResponseTime - forwardRequestTime); 40410012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[respondingMach]->sample( 4059773Snilay@cs.wisc.edu completionTime - firstResponseTime); 4069773Snilay@cs.wisc.edu } else { 4079773Snilay@cs.wisc.edu m_IncompleteTimes[respondingMach]++; 4089773Snilay@cs.wisc.edu } 4099773Snilay@cs.wisc.edu } 4109773Snilay@cs.wisc.edu } else { 41110012Snilay@cs.wisc.edu m_hitLatencyHist.sample(cycles); 41210012Snilay@cs.wisc.edu m_hitTypeLatencyHist[type]->sample(cycles); 4139773Snilay@cs.wisc.edu 4149773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 41510012Snilay@cs.wisc.edu m_hitMachLatencyHist[respondingMach]->sample(cycles); 41610012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles); 4179773Snilay@cs.wisc.edu } 4189773Snilay@cs.wisc.edu } 4197546SBrad.Beckmann@amd.com} 4207546SBrad.Beckmann@amd.com 4217546SBrad.Beckmann@amd.comvoid 4229773Snilay@cs.wisc.eduSequencer::writeCallback(const Address& address, DataBlock& data, 4239773Snilay@cs.wisc.edu const bool externalHit, const MachineType mach, 4249773Snilay@cs.wisc.edu const Cycles initialRequestTime, 4259773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 4269773Snilay@cs.wisc.edu const Cycles firstResponseTime) 4277565SBrad.Beckmann@amd.com{ 4287039Snate@binkert.org assert(address == line_address(address)); 4297455Snate@binkert.org assert(m_writeRequestTable.count(line_address(address))); 4306145Snate@binkert.org 4317455Snate@binkert.org RequestTable::iterator i = m_writeRequestTable.find(address); 4327455Snate@binkert.org assert(i != m_writeRequestTable.end()); 4337455Snate@binkert.org SequencerRequest* request = i->second; 4346145Snate@binkert.org 4357455Snate@binkert.org m_writeRequestTable.erase(i); 4367455Snate@binkert.org markRemoved(); 4376846Spdudnik@cs.wisc.edu 4388615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_ST) || 4398615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_ATOMIC) || 4408615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Read) || 4418615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Write) || 4428615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Load_Linked) || 4438615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Store_Conditional) || 4448615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Read) || 4458615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Write) || 4468615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_FLUSH)); 4478184Ssomayeh@cs.wisc.edu 4487550SBrad.Beckmann@amd.com // 4497550SBrad.Beckmann@amd.com // For Alpha, properly handle LL, SC, and write requests with respect to 4507550SBrad.Beckmann@amd.com // locked cache blocks. 4517550SBrad.Beckmann@amd.com // 4528171Stushar@csail.mit.edu // Not valid for Network_test protocl 4538171Stushar@csail.mit.edu // 4548171Stushar@csail.mit.edu bool success = true; 4558171Stushar@csail.mit.edu if(!m_usingNetworkTester) 4568171Stushar@csail.mit.edu success = handleLlsc(address, request); 4577550SBrad.Beckmann@amd.com 4588615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Locked_RMW_Read) { 4597039Snate@binkert.org m_controller->blockOnQueue(address, m_mandatory_q_ptr); 4608615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { 4617039Snate@binkert.org m_controller->unblock(address); 4627039Snate@binkert.org } 4636863Sdrh5@cs.wisc.edu 4649773Snilay@cs.wisc.edu hitCallback(request, data, success, mach, externalHit, 4657565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 4666145Snate@binkert.org} 4676145Snate@binkert.org 4687039Snate@binkert.orgvoid 4699773Snilay@cs.wisc.eduSequencer::readCallback(const Address& address, DataBlock& data, 4709773Snilay@cs.wisc.edu bool externalHit, const MachineType mach, 4719507Snilay@cs.wisc.edu Cycles initialRequestTime, 4729507Snilay@cs.wisc.edu Cycles forwardRequestTime, 4739507Snilay@cs.wisc.edu Cycles firstResponseTime) 4747565SBrad.Beckmann@amd.com{ 4757039Snate@binkert.org assert(address == line_address(address)); 4767455Snate@binkert.org assert(m_readRequestTable.count(line_address(address))); 4776145Snate@binkert.org 4787455Snate@binkert.org RequestTable::iterator i = m_readRequestTable.find(address); 4797455Snate@binkert.org assert(i != m_readRequestTable.end()); 4807455Snate@binkert.org SequencerRequest* request = i->second; 4817455Snate@binkert.org 4827455Snate@binkert.org m_readRequestTable.erase(i); 4837455Snate@binkert.org markRemoved(); 4846145Snate@binkert.org 4858615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_LD) || 4868615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_IFETCH)); 4876285Snate@binkert.org 4889773Snilay@cs.wisc.edu hitCallback(request, data, true, mach, externalHit, 4897565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 4906145Snate@binkert.org} 4916145Snate@binkert.org 4927039Snate@binkert.orgvoid 4939773Snilay@cs.wisc.eduSequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, 4949773Snilay@cs.wisc.edu bool llscSuccess, 4959773Snilay@cs.wisc.edu const MachineType mach, const bool externalHit, 4969773Snilay@cs.wisc.edu const Cycles initialRequestTime, 4979773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 4989773Snilay@cs.wisc.edu const Cycles firstResponseTime) 4997039Snate@binkert.org{ 5008615Snilay@cs.wisc.edu PacketPtr pkt = srequest->pkt; 5018615Snilay@cs.wisc.edu Address request_address(pkt->getAddr()); 5028615Snilay@cs.wisc.edu Address request_line_address(pkt->getAddr()); 5037039Snate@binkert.org request_line_address.makeLineAddress(); 5048615Snilay@cs.wisc.edu RubyRequestType type = srequest->m_type; 5059507Snilay@cs.wisc.edu Cycles issued_time = srequest->issue_time; 5066145Snate@binkert.org 5077039Snate@binkert.org // Set this cache entry to the most recently used 5087039Snate@binkert.org if (type == RubyRequestType_IFETCH) { 5098828Snilay@cs.wisc.edu m_instCache_ptr->setMRU(request_line_address); 5107039Snate@binkert.org } else { 5118828Snilay@cs.wisc.edu m_dataCache_ptr->setMRU(request_line_address); 5127039Snate@binkert.org } 5136145Snate@binkert.org 5149465Snilay@cs.wisc.edu assert(curCycle() >= issued_time); 5159773Snilay@cs.wisc.edu Cycles total_latency = curCycle() - issued_time; 5166145Snate@binkert.org 5179773Snilay@cs.wisc.edu // Profile the latency for all demand accesses. 5189773Snilay@cs.wisc.edu recordMissLatency(total_latency, type, mach, externalHit, issued_time, 5199773Snilay@cs.wisc.edu initialRequestTime, forwardRequestTime, 5209773Snilay@cs.wisc.edu firstResponseTime, curCycle()); 5216285Snate@binkert.org 5229773Snilay@cs.wisc.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n", 5239773Snilay@cs.wisc.edu curTick(), m_version, "Seq", 5249773Snilay@cs.wisc.edu llscSuccess ? "Done" : "SC_Failed", "", "", 5259773Snilay@cs.wisc.edu request_address, total_latency); 5266285Snate@binkert.org 5277039Snate@binkert.org // update the data 5288688Snilay@cs.wisc.edu if (g_system_ptr->m_warmup_enabled) { 5298688Snilay@cs.wisc.edu assert(pkt->getPtr<uint8_t>(false) != NULL); 5308688Snilay@cs.wisc.edu data.setData(pkt->getPtr<uint8_t>(false), 5318688Snilay@cs.wisc.edu request_address.getOffset(), pkt->getSize()); 5328688Snilay@cs.wisc.edu } else if (pkt->getPtr<uint8_t>(true) != NULL) { 5337039Snate@binkert.org if ((type == RubyRequestType_LD) || 5347039Snate@binkert.org (type == RubyRequestType_IFETCH) || 5357039Snate@binkert.org (type == RubyRequestType_RMW_Read) || 5367908Shestness@cs.utexas.edu (type == RubyRequestType_Locked_RMW_Read) || 5377907Shestness@cs.utexas.edu (type == RubyRequestType_Load_Linked)) { 5388615Snilay@cs.wisc.edu memcpy(pkt->getPtr<uint8_t>(true), 5398615Snilay@cs.wisc.edu data.getData(request_address.getOffset(), pkt->getSize()), 5408615Snilay@cs.wisc.edu pkt->getSize()); 5417039Snate@binkert.org } else { 5428615Snilay@cs.wisc.edu data.setData(pkt->getPtr<uint8_t>(true), 5438615Snilay@cs.wisc.edu request_address.getOffset(), pkt->getSize()); 5447039Snate@binkert.org } 5456285Snate@binkert.org } else { 5467039Snate@binkert.org DPRINTF(MemoryAccess, 5477039Snate@binkert.org "WARNING. Data not transfered from Ruby to M5 for type %s\n", 5487039Snate@binkert.org RubyRequestType_to_string(type)); 5497039Snate@binkert.org } 5507023SBrad.Beckmann@amd.com 5517039Snate@binkert.org // If using the RubyTester, update the RubyTester sender state's 5527039Snate@binkert.org // subBlock with the recieved data. The tester will later access 5537039Snate@binkert.org // this state. 5547039Snate@binkert.org if (m_usingRubyTester) { 5557039Snate@binkert.org RubyTester::SenderState* testerSenderState = 55610089Sandreas.hansson@arm.com pkt->findNextSenderState<RubyTester::SenderState>(); 55710089Sandreas.hansson@arm.com assert(testerSenderState); 5589542Sandreas.hansson@arm.com testerSenderState->subBlock.mergeFrom(data); 5597039Snate@binkert.org } 5607023SBrad.Beckmann@amd.com 5617039Snate@binkert.org delete srequest; 5628688Snilay@cs.wisc.edu 5638688Snilay@cs.wisc.edu if (g_system_ptr->m_warmup_enabled) { 5649632Sjthestness@gmail.com assert(pkt->req); 5659632Sjthestness@gmail.com delete pkt->req; 5668688Snilay@cs.wisc.edu delete pkt; 5678688Snilay@cs.wisc.edu g_system_ptr->m_cache_recorder->enqueueNextFetchRequest(); 5688688Snilay@cs.wisc.edu } else if (g_system_ptr->m_cooldown_enabled) { 5698688Snilay@cs.wisc.edu delete pkt; 5708688Snilay@cs.wisc.edu g_system_ptr->m_cache_recorder->enqueueNextFlushRequest(); 5718688Snilay@cs.wisc.edu } else { 5728688Snilay@cs.wisc.edu ruby_hit_callback(pkt); 5738688Snilay@cs.wisc.edu } 5746285Snate@binkert.org} 5756285Snate@binkert.org 5767039Snate@binkert.orgbool 5777039Snate@binkert.orgSequencer::empty() const 5787039Snate@binkert.org{ 5797455Snate@binkert.org return m_writeRequestTable.empty() && m_readRequestTable.empty(); 5806145Snate@binkert.org} 5816145Snate@binkert.org 5827039Snate@binkert.orgRequestStatus 5838615Snilay@cs.wisc.eduSequencer::makeRequest(PacketPtr pkt) 5847039Snate@binkert.org{ 5858615Snilay@cs.wisc.edu if (m_outstanding_count >= m_max_outstanding_requests) { 5868615Snilay@cs.wisc.edu return RequestStatus_BufferFull; 5878615Snilay@cs.wisc.edu } 5888615Snilay@cs.wisc.edu 5898615Snilay@cs.wisc.edu RubyRequestType primary_type = RubyRequestType_NULL; 5908615Snilay@cs.wisc.edu RubyRequestType secondary_type = RubyRequestType_NULL; 5918615Snilay@cs.wisc.edu 5928615Snilay@cs.wisc.edu if (pkt->isLLSC()) { 5938615Snilay@cs.wisc.edu // 5948615Snilay@cs.wisc.edu // Alpha LL/SC instructions need to be handled carefully by the cache 5958615Snilay@cs.wisc.edu // coherence protocol to ensure they follow the proper semantics. In 5968615Snilay@cs.wisc.edu // particular, by identifying the operations as atomic, the protocol 5978615Snilay@cs.wisc.edu // should understand that migratory sharing optimizations should not 5988615Snilay@cs.wisc.edu // be performed (i.e. a load between the LL and SC should not steal 5998615Snilay@cs.wisc.edu // away exclusive permission). 6008615Snilay@cs.wisc.edu // 6018615Snilay@cs.wisc.edu if (pkt->isWrite()) { 6028615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing SC\n"); 6038615Snilay@cs.wisc.edu primary_type = RubyRequestType_Store_Conditional; 6048615Snilay@cs.wisc.edu } else { 6058615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing LL\n"); 6068615Snilay@cs.wisc.edu assert(pkt->isRead()); 6078615Snilay@cs.wisc.edu primary_type = RubyRequestType_Load_Linked; 6088615Snilay@cs.wisc.edu } 6098615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ATOMIC; 6108615Snilay@cs.wisc.edu } else if (pkt->req->isLocked()) { 6118615Snilay@cs.wisc.edu // 6128615Snilay@cs.wisc.edu // x86 locked instructions are translated to store cache coherence 6138615Snilay@cs.wisc.edu // requests because these requests should always be treated as read 6148615Snilay@cs.wisc.edu // exclusive operations and should leverage any migratory sharing 6158615Snilay@cs.wisc.edu // optimization built into the protocol. 6168615Snilay@cs.wisc.edu // 6178615Snilay@cs.wisc.edu if (pkt->isWrite()) { 6188615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); 6198615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Write; 6208615Snilay@cs.wisc.edu } else { 6218615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); 6228615Snilay@cs.wisc.edu assert(pkt->isRead()); 6238615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Read; 6248615Snilay@cs.wisc.edu } 6258615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 6268615Snilay@cs.wisc.edu } else { 6278615Snilay@cs.wisc.edu if (pkt->isRead()) { 6288615Snilay@cs.wisc.edu if (pkt->req->isInstFetch()) { 6298615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_IFETCH; 6308615Snilay@cs.wisc.edu } else { 6318615Snilay@cs.wisc.edu bool storeCheck = false; 63210467Sandreas.hansson@arm.com // only X86 need the store check 63310467Sandreas.hansson@arm.com if (system->getArch() == Arch::X86ISA) { 63410467Sandreas.hansson@arm.com uint32_t flags = pkt->req->getFlags(); 63510467Sandreas.hansson@arm.com storeCheck = flags & 63610467Sandreas.hansson@arm.com (X86ISA::StoreCheck << X86ISA::FlagShift); 63710467Sandreas.hansson@arm.com } 6388615Snilay@cs.wisc.edu if (storeCheck) { 6398615Snilay@cs.wisc.edu primary_type = RubyRequestType_RMW_Read; 6408615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 6418615Snilay@cs.wisc.edu } else { 6428615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_LD; 6438615Snilay@cs.wisc.edu } 6448615Snilay@cs.wisc.edu } 6458615Snilay@cs.wisc.edu } else if (pkt->isWrite()) { 6468615Snilay@cs.wisc.edu // 6478615Snilay@cs.wisc.edu // Note: M5 packets do not differentiate ST from RMW_Write 6488615Snilay@cs.wisc.edu // 6498615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_ST; 6508615Snilay@cs.wisc.edu } else if (pkt->isFlush()) { 6518615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_FLUSH; 6528615Snilay@cs.wisc.edu } else { 6538615Snilay@cs.wisc.edu panic("Unsupported ruby packet type\n"); 6548615Snilay@cs.wisc.edu } 6558615Snilay@cs.wisc.edu } 6568615Snilay@cs.wisc.edu 6578615Snilay@cs.wisc.edu RequestStatus status = insertRequest(pkt, primary_type); 6587039Snate@binkert.org if (status != RequestStatus_Ready) 6597039Snate@binkert.org return status; 6606349Spdudnik@gmail.com 6618615Snilay@cs.wisc.edu issueRequest(pkt, secondary_type); 6626145Snate@binkert.org 6637039Snate@binkert.org // TODO: issue hardware prefetches here 6647039Snate@binkert.org return RequestStatus_Issued; 6656145Snate@binkert.org} 6666145Snate@binkert.org 6677039Snate@binkert.orgvoid 6688615Snilay@cs.wisc.eduSequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) 6697039Snate@binkert.org{ 6709216Sandreas.hansson@arm.com assert(pkt != NULL); 6718615Snilay@cs.wisc.edu int proc_id = -1; 6729216Sandreas.hansson@arm.com if (pkt->req->hasContextId()) { 6738615Snilay@cs.wisc.edu proc_id = pkt->req->contextId(); 6747039Snate@binkert.org } 6756285Snate@binkert.org 6768615Snilay@cs.wisc.edu // If valid, copy the pc to the ruby request 6778615Snilay@cs.wisc.edu Addr pc = 0; 6788615Snilay@cs.wisc.edu if (pkt->req->hasPC()) { 6798615Snilay@cs.wisc.edu pc = pkt->req->getPC(); 6807039Snate@binkert.org } 6816285Snate@binkert.org 6829508Snilay@cs.wisc.edu RubyRequest *msg = new RubyRequest(clockEdge(), pkt->getAddr(), 6838615Snilay@cs.wisc.edu pkt->getPtr<uint8_t>(true), 6848615Snilay@cs.wisc.edu pkt->getSize(), pc, secondary_type, 6858615Snilay@cs.wisc.edu RubyAccessMode_Supervisor, pkt, 6868188SLisa.Hsu@amd.com PrefetchBit_No, proc_id); 6876285Snate@binkert.org 6888266Sksewell@umich.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n", 6898266Sksewell@umich.edu curTick(), m_version, "Seq", "Begin", "", "", 6908615Snilay@cs.wisc.edu msg->getPhysicalAddress(), 6918615Snilay@cs.wisc.edu RubyRequestType_to_string(secondary_type)); 6926285Snate@binkert.org 6939499Snilay@cs.wisc.edu Cycles latency(0); // initialzed to an null value 6946285Snate@binkert.org 6958615Snilay@cs.wisc.edu if (secondary_type == RubyRequestType_IFETCH) 6967039Snate@binkert.org latency = m_instCache_ptr->getLatency(); 6977039Snate@binkert.org else 6987039Snate@binkert.org latency = m_dataCache_ptr->getLatency(); 6996285Snate@binkert.org 7007039Snate@binkert.org // Send the message to the cache controller 7017039Snate@binkert.org assert(latency > 0); 7026145Snate@binkert.org 7037039Snate@binkert.org assert(m_mandatory_q_ptr != NULL); 7047039Snate@binkert.org m_mandatory_q_ptr->enqueue(msg, latency); 7056145Snate@binkert.org} 7066145Snate@binkert.org 7077455Snate@binkert.orgtemplate <class KEY, class VALUE> 7087455Snate@binkert.orgstd::ostream & 7097455Snate@binkert.orgoperator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) 7107455Snate@binkert.org{ 7117455Snate@binkert.org typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); 7127455Snate@binkert.org typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); 7137455Snate@binkert.org 7147455Snate@binkert.org out << "["; 7157455Snate@binkert.org for (; i != end; ++i) 7167455Snate@binkert.org out << " " << i->first << "=" << i->second; 7177455Snate@binkert.org out << " ]"; 7187455Snate@binkert.org 7197455Snate@binkert.org return out; 7207455Snate@binkert.org} 7217455Snate@binkert.org 7227039Snate@binkert.orgvoid 7237039Snate@binkert.orgSequencer::print(ostream& out) const 7247039Snate@binkert.org{ 7257039Snate@binkert.org out << "[Sequencer: " << m_version 7267039Snate@binkert.org << ", outstanding requests: " << m_outstanding_count 7277039Snate@binkert.org << ", read request table: " << m_readRequestTable 7287039Snate@binkert.org << ", write request table: " << m_writeRequestTable 7297039Snate@binkert.org << "]"; 7307039Snate@binkert.org} 7317039Snate@binkert.org 7327039Snate@binkert.org// this can be called from setState whenever coherence permissions are 7337039Snate@binkert.org// upgraded when invoked, coherence violations will be checked for the 7347039Snate@binkert.org// given block 7357039Snate@binkert.orgvoid 7367039Snate@binkert.orgSequencer::checkCoherence(const Address& addr) 7377039Snate@binkert.org{ 7386145Snate@binkert.org#ifdef CHECK_COHERENCE 7397039Snate@binkert.org g_system_ptr->checkGlobalCoherenceInvariant(addr); 7406145Snate@binkert.org#endif 7416145Snate@binkert.org} 7428717Snilay@cs.wisc.edu 7438717Snilay@cs.wisc.eduvoid 7449104Shestness@cs.utexas.eduSequencer::recordRequestType(SequencerRequestType requestType) { 7459104Shestness@cs.utexas.edu DPRINTF(RubyStats, "Recorded statistic: %s\n", 7469104Shestness@cs.utexas.edu SequencerRequestType_to_string(requestType)); 7479104Shestness@cs.utexas.edu} 7489104Shestness@cs.utexas.edu 7499104Shestness@cs.utexas.edu 7509104Shestness@cs.utexas.eduvoid 7518717Snilay@cs.wisc.eduSequencer::evictionCallback(const Address& address) 7528717Snilay@cs.wisc.edu{ 7538717Snilay@cs.wisc.edu ruby_eviction_callback(address); 7548717Snilay@cs.wisc.edu} 75510012Snilay@cs.wisc.edu 75610012Snilay@cs.wisc.eduvoid 75710012Snilay@cs.wisc.eduSequencer::regStats() 75810012Snilay@cs.wisc.edu{ 75910012Snilay@cs.wisc.edu m_store_waiting_on_load 76010012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_load") 76110012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending load") 76210012Snilay@cs.wisc.edu .flags(Stats::nozero); 76310012Snilay@cs.wisc.edu m_store_waiting_on_store 76410012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_store") 76510012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending store") 76610012Snilay@cs.wisc.edu .flags(Stats::nozero); 76710012Snilay@cs.wisc.edu m_load_waiting_on_load 76810012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_load") 76910012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending load") 77010012Snilay@cs.wisc.edu .flags(Stats::nozero); 77110012Snilay@cs.wisc.edu m_load_waiting_on_store 77210012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_store") 77310012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending store") 77410012Snilay@cs.wisc.edu .flags(Stats::nozero); 77510012Snilay@cs.wisc.edu 77610012Snilay@cs.wisc.edu // These statistical variables are not for display. 77710012Snilay@cs.wisc.edu // The profiler will collate these across different 77810012Snilay@cs.wisc.edu // sequencers and display those collated statistics. 77910012Snilay@cs.wisc.edu m_outstandReqHist.init(10); 78010012Snilay@cs.wisc.edu m_latencyHist.init(10); 78110012Snilay@cs.wisc.edu m_hitLatencyHist.init(10); 78210012Snilay@cs.wisc.edu m_missLatencyHist.init(10); 78310012Snilay@cs.wisc.edu 78410012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 78510012Snilay@cs.wisc.edu m_typeLatencyHist.push_back(new Stats::Histogram()); 78610012Snilay@cs.wisc.edu m_typeLatencyHist[i]->init(10); 78710012Snilay@cs.wisc.edu 78810012Snilay@cs.wisc.edu m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 78910012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->init(10); 79010012Snilay@cs.wisc.edu 79110012Snilay@cs.wisc.edu m_missTypeLatencyHist.push_back(new Stats::Histogram()); 79210012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->init(10); 79310012Snilay@cs.wisc.edu } 79410012Snilay@cs.wisc.edu 79510012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 79610012Snilay@cs.wisc.edu m_hitMachLatencyHist.push_back(new Stats::Histogram()); 79710012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->init(10); 79810012Snilay@cs.wisc.edu 79910012Snilay@cs.wisc.edu m_missMachLatencyHist.push_back(new Stats::Histogram()); 80010012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->init(10); 80110012Snilay@cs.wisc.edu 80210012Snilay@cs.wisc.edu m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 80310012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->init(10); 80410012Snilay@cs.wisc.edu 80510012Snilay@cs.wisc.edu m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 80610012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->init(10); 80710012Snilay@cs.wisc.edu 80810012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 80910012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->init(10); 81010012Snilay@cs.wisc.edu 81110012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 81210012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->init(10); 81310012Snilay@cs.wisc.edu } 81410012Snilay@cs.wisc.edu 81510012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 81610012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 81710012Snilay@cs.wisc.edu m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 81810012Snilay@cs.wisc.edu 81910012Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 82010012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 82110012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->init(10); 82210012Snilay@cs.wisc.edu 82310012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 82410012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->init(10); 82510012Snilay@cs.wisc.edu } 82610012Snilay@cs.wisc.edu } 82710012Snilay@cs.wisc.edu} 828