DMASequencer.hh revision 6825
14309Sgblack@eecs.umich.edu 24309Sgblack@eecs.umich.edu#ifndef DMASEQUENCER_H 34309Sgblack@eecs.umich.edu#define DMASEQUENCER_H 44309Sgblack@eecs.umich.edu 54309Sgblack@eecs.umich.edu#include <ostream> 64309Sgblack@eecs.umich.edu#include "mem/ruby/common/DataBlock.hh" 74309Sgblack@eecs.umich.edu#include "mem/ruby/system/RubyPort.hh" 84309Sgblack@eecs.umich.edu 94309Sgblack@eecs.umich.edustruct DMARequest { 104309Sgblack@eecs.umich.edu uint64_t start_paddr; 114309Sgblack@eecs.umich.edu int len; 124309Sgblack@eecs.umich.edu bool write; 134309Sgblack@eecs.umich.edu int bytes_completed; 144309Sgblack@eecs.umich.edu int bytes_issued; 154309Sgblack@eecs.umich.edu uint8* data; 164309Sgblack@eecs.umich.edu int64_t id; 174309Sgblack@eecs.umich.edu}; 184309Sgblack@eecs.umich.edu 194309Sgblack@eecs.umich.educlass MessageBuffer; 204309Sgblack@eecs.umich.educlass AbstractController; 214309Sgblack@eecs.umich.edu 224309Sgblack@eecs.umich.educlass DMASequencer :public RubyPort { 234309Sgblack@eecs.umich.edupublic: 244309Sgblack@eecs.umich.edu DMASequencer(const string & name); 254309Sgblack@eecs.umich.edu void init(const vector<string> & argv); 264309Sgblack@eecs.umich.edu /* external interface */ 274309Sgblack@eecs.umich.edu int64_t makeRequest(const RubyRequest & request); 284309Sgblack@eecs.umich.edu bool isReady(const RubyRequest & request, bool dont_set = false) { assert(0); return false;}; 294309Sgblack@eecs.umich.edu // void issueRequest(uint64_t paddr, uint8* data, int len, bool rw); 304309Sgblack@eecs.umich.edu bool busy() { return m_is_busy;} 314309Sgblack@eecs.umich.edu 324309Sgblack@eecs.umich.edu /* SLICC callback */ 334309Sgblack@eecs.umich.edu void dataCallback(const DataBlock & dblk); 344309Sgblack@eecs.umich.edu void ackCallback(); 354309Sgblack@eecs.umich.edu 364309Sgblack@eecs.umich.edu void printConfig(std::ostream & out); 374309Sgblack@eecs.umich.edu 384309Sgblack@eecs.umich.eduprivate: 394309Sgblack@eecs.umich.edu void issueNext(); 404309Sgblack@eecs.umich.edu 414309Sgblack@eecs.umich.eduprivate: 424309Sgblack@eecs.umich.edu int m_version; 434309Sgblack@eecs.umich.edu AbstractController* m_controller; 444309Sgblack@eecs.umich.edu bool m_is_busy; 454309Sgblack@eecs.umich.edu uint64_t m_data_block_mask; 464309Sgblack@eecs.umich.edu DMARequest active_request; 474309Sgblack@eecs.umich.edu int num_active_requests; 484309Sgblack@eecs.umich.edu MessageBuffer* m_mandatory_q_ptr; 494309Sgblack@eecs.umich.edu}; 504309Sgblack@eecs.umich.edu 514309Sgblack@eecs.umich.edu#endif // DMACONTROLLER_H 524309Sgblack@eecs.umich.edu