DMASequencer.hh revision 6368 
1
2#ifndef DMASEQUENCER_H
3#define DMASEQUENCER_H
4
5#include <ostream>
6#include "mem/ruby/common/DataBlock.hh"
7#include "mem/ruby/system/RubyPort.hh"
8
9struct DMARequest {
10  uint64_t start_paddr;
11  int len;
12  bool write;
13  int bytes_completed;
14  int bytes_issued;
15  uint8* data;
16  int64_t id;
17};
18
19class MessageBuffer;
20class AbstractController;
21
22class DMASequencer :public RubyPort {
23public:
24  DMASequencer(const string & name);
25  void init(const vector<string> & argv);
26  /* external interface */
27  int64_t makeRequest(const RubyRequest & request);
28  //  void issueRequest(uint64_t paddr, uint8* data, int len, bool rw);
29  bool busy() { return m_is_busy;}
30
31  /* SLICC callback */
32  void dataCallback(const DataBlock & dblk);
33  void ackCallback();
34
35  void printConfig(std::ostream & out);
36
37private:
38  void issueNext();
39
40private:
41  int m_version;
42  AbstractController* m_controller;
43  bool m_is_busy;
44  uint64_t m_data_block_mask;
45  DMARequest active_request;
46  int num_active_requests;
47  MessageBuffer* m_mandatory_q_ptr;
48};
49
50#endif // DMACONTROLLER_H
51