DMASequencer.cc revision 7908:4e83ebb67794 
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "mem/protocol/SequencerMsg.hh"
30#include "mem/protocol/SequencerRequestType.hh"
31#include "mem/ruby/buffers/MessageBuffer.hh"
32#include "mem/ruby/slicc_interface/AbstractController.hh"
33#include "mem/ruby/system/DMASequencer.hh"
34#include "mem/ruby/system/System.hh"
35
36DMASequencer::DMASequencer(const Params *p)
37    : RubyPort(p)
38{
39}
40
41void
42DMASequencer::init()
43{
44    RubyPort::init();
45    m_is_busy = false;
46    m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
47}
48
49RequestStatus
50DMASequencer::makeRequest(const RubyRequest &request)
51{
52    if (m_is_busy) {
53        return RequestStatus_BufferFull;
54    }
55
56    uint64_t paddr = request.paddr;
57    uint8_t* data = request.data;
58    int len = request.len;
59    bool write = false;
60    switch(request.type) {
61      case RubyRequestType_LD:
62        write = false;
63        break;
64      case RubyRequestType_ST:
65        write = true;
66        break;
67      case RubyRequestType_NULL:
68      case RubyRequestType_IFETCH:
69      case RubyRequestType_Load_Linked:
70      case RubyRequestType_Store_Conditional:
71      case RubyRequestType_RMW_Read:
72      case RubyRequestType_RMW_Write:
73      case RubyRequestType_Locked_RMW_Read:
74      case RubyRequestType_Locked_RMW_Write:
75      case RubyRequestType_NUM:
76        panic("DMASequencer::makeRequest does not support RubyRequestType");
77        return RequestStatus_NULL;
78    }
79
80    assert(!m_is_busy);  // only support one outstanding DMA request
81    m_is_busy = true;
82
83    active_request.start_paddr = paddr;
84    active_request.write = write;
85    active_request.data = data;
86    active_request.len = len;
87    active_request.bytes_completed = 0;
88    active_request.bytes_issued = 0;
89    active_request.pkt = request.pkt;
90
91    SequencerMsg *msg = new SequencerMsg;
92    msg->getPhysicalAddress() = Address(paddr);
93    msg->getLineAddress() = line_address(msg->getPhysicalAddress());
94    msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
95    int offset = paddr & m_data_block_mask;
96
97    msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
98        len : RubySystem::getBlockSizeBytes() - offset;
99
100    if (write) {
101        msg->getDataBlk().setData(data, offset, msg->getLen());
102    }
103
104    assert(m_mandatory_q_ptr != NULL);
105    m_mandatory_q_ptr->enqueue(msg);
106    active_request.bytes_issued += msg->getLen();
107
108    return RequestStatus_Issued;
109}
110
111void
112DMASequencer::issueNext()
113{
114    assert(m_is_busy == true);
115    active_request.bytes_completed = active_request.bytes_issued;
116    if (active_request.len == active_request.bytes_completed) {
117        DPRINTF(RubyDma, "DMA request completed\n");
118        ruby_hit_callback(active_request.pkt);
119        m_is_busy = false;
120        return;
121    }
122
123    SequencerMsg *msg = new SequencerMsg;
124    msg->getPhysicalAddress() = Address(active_request.start_paddr +
125                                       active_request.bytes_completed);
126
127    assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
128    msg->getLineAddress() = line_address(msg->getPhysicalAddress());
129
130    msg->getType() = (active_request.write ? SequencerRequestType_ST :
131                     SequencerRequestType_LD);
132
133    msg->getLen() =
134        (active_request.len -
135         active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
136         active_request.len - active_request.bytes_completed :
137         RubySystem::getBlockSizeBytes());
138
139    if (active_request.write) {
140        msg->getDataBlk().
141            setData(&active_request.data[active_request.bytes_completed],
142                    0, msg->getLen());
143        msg->getType() = SequencerRequestType_ST;
144    } else {
145        msg->getType() = SequencerRequestType_LD;
146    }
147
148    assert(m_mandatory_q_ptr != NULL);
149    m_mandatory_q_ptr->enqueue(msg);
150    active_request.bytes_issued += msg->getLen();
151    DPRINTF(RubyDma, "Next DMA segment issued to the DMA cntrl\n");
152}
153
154void
155DMASequencer::dataCallback(const DataBlock & dblk)
156{
157    assert(m_is_busy == true);
158    int len = active_request.bytes_issued - active_request.bytes_completed;
159    int offset = 0;
160    if (active_request.bytes_completed == 0)
161        offset = active_request.start_paddr & m_data_block_mask;
162    assert(active_request.write == false);
163    memcpy(&active_request.data[active_request.bytes_completed],
164           dblk.getData(offset, len), len);
165    issueNext();
166}
167
168void
169DMASequencer::ackCallback()
170{
171    issueNext();
172}
173
174void
175DMASequencer::printConfig(std::ostream & out)
176{
177}
178
179DMASequencer *
180DMASequencerParams::create()
181{
182    return new DMASequencer(this);
183}
184