DMASequencer.cc revision 7008:90c097fb76e1 
1/*
2 * Copyright (c) 2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "mem/ruby/system/DMASequencer.hh"
30#include "mem/ruby/buffers/MessageBuffer.hh"
31#include "mem/ruby/slicc_interface/AbstractController.hh"
32
33/* SLICC generated types */
34#include "mem/protocol/SequencerMsg.hh"
35#include "mem/protocol/SequencerRequestType.hh"
36#include "mem/ruby/system/System.hh"
37
38//
39// Fix me: This code needs comments!
40//
41
42DMASequencer::DMASequencer(const Params *p)
43  : RubyPort(p)
44{
45}
46
47void DMASequencer::init()
48{
49  RubyPort::init();
50  m_is_busy = false;
51  m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
52}
53
54RequestStatus DMASequencer::makeRequest(const RubyRequest & request)
55{
56  uint64_t paddr = request.paddr;
57  uint8_t* data = request.data;
58  int len = request.len;
59  bool write = false;
60  switch(request.type) {
61  case RubyRequestType_LD:
62    write = false;
63    break;
64  case RubyRequestType_ST:
65    write = true;
66    break;
67  case RubyRequestType_NULL:
68  case RubyRequestType_IFETCH:
69  case RubyRequestType_Locked_Read:
70  case RubyRequestType_Locked_Write:
71  case RubyRequestType_RMW_Read:
72  case RubyRequestType_RMW_Write:
73  case RubyRequestType_NUM:
74    panic("DMASequencer::makeRequest does not support the RubyRequestType");
75    return RequestStatus_NULL;
76  }
77
78  assert(!m_is_busy);  // only support one outstanding DMA request
79  m_is_busy = true;
80
81  active_request.start_paddr = paddr;
82  active_request.write = write;
83  active_request.data = data;
84  active_request.len = len;
85  active_request.bytes_completed = 0;
86  active_request.bytes_issued = 0;
87  active_request.pkt = request.pkt;
88
89  SequencerMsg msg;
90  msg.getPhysicalAddress() = Address(paddr);
91  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
92  msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
93  int offset = paddr & m_data_block_mask;
94
95  msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
96    len :
97    RubySystem::getBlockSizeBytes() - offset;
98
99  if (write) {
100    msg.getDataBlk().setData(data, offset, msg.getLen());
101  }
102
103  assert(m_mandatory_q_ptr != NULL);
104  m_mandatory_q_ptr->enqueue(msg);
105  active_request.bytes_issued += msg.getLen();
106
107  return RequestStatus_Issued;
108}
109
110void DMASequencer::issueNext()
111{
112  assert(m_is_busy == true);
113  active_request.bytes_completed = active_request.bytes_issued;
114  if (active_request.len == active_request.bytes_completed) {
115    ruby_hit_callback(active_request.pkt);
116    m_is_busy = false;
117    return;
118  }
119
120  SequencerMsg msg;
121  msg.getPhysicalAddress() = Address(active_request.start_paddr +
122                                     active_request.bytes_completed);
123
124  assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
125  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
126
127  msg.getType() = (active_request.write ? SequencerRequestType_ST :
128		   SequencerRequestType_LD);
129
130  msg.getLen() = (active_request.len -
131		  active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
132		  active_request.len - active_request.bytes_completed :
133		  RubySystem::getBlockSizeBytes());
134
135  if (active_request.write) {
136    msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
137			     0, msg.getLen());
138    msg.getType() = SequencerRequestType_ST;
139  } else {
140    msg.getType() = SequencerRequestType_LD;
141  }
142
143  assert(m_mandatory_q_ptr != NULL);
144  m_mandatory_q_ptr->enqueue(msg);
145  active_request.bytes_issued += msg.getLen();
146}
147
148void DMASequencer::dataCallback(const DataBlock & dblk)
149{
150  assert(m_is_busy == true);
151  int len = active_request.bytes_issued - active_request.bytes_completed;
152  int offset = 0;
153  if (active_request.bytes_completed == 0)
154    offset = active_request.start_paddr & m_data_block_mask;
155  assert( active_request.write == false );
156  memcpy(&active_request.data[active_request.bytes_completed],
157	 dblk.getData(offset, len), len);
158  issueNext();
159}
160
161void DMASequencer::ackCallback()
162{
163  issueNext();
164}
165
166void DMASequencer::printConfig(ostream & out)
167{
168
169}
170
171
172DMASequencer *
173DMASequencerParams::create()
174{
175    return new DMASequencer(this);
176}
177