DMASequencer.cc revision 6876:a658c315512c 
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/SequencerMsg.hh"
8#include "mem/protocol/SequencerRequestType.hh"
9#include "mem/ruby/system/System.hh"
10
11DMASequencer::DMASequencer(const Params *p)
12  : RubyPort(p)
13{
14}
15
16void DMASequencer::init()
17{
18  m_is_busy = false;
19  m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
20}
21
22int64_t DMASequencer::makeRequest(const RubyRequest & request)
23{
24  uint64_t paddr = request.paddr;
25  uint8_t* data = request.data;
26  int len = request.len;
27  bool write = false;
28  switch(request.type) {
29  case RubyRequestType_LD:
30    write = false;
31    break;
32  case RubyRequestType_ST:
33    write = true;
34    break;
35  case RubyRequestType_NULL:
36  case RubyRequestType_IFETCH:
37  case RubyRequestType_Locked_Read:
38  case RubyRequestType_Locked_Write:
39  case RubyRequestType_RMW_Read:
40  case RubyRequestType_RMW_Write:
41  case RubyRequestType_NUM:
42    assert(0);
43  }
44
45  assert(!m_is_busy);  // only support one outstanding DMA request
46  m_is_busy = true;
47
48  active_request.start_paddr = paddr;
49  active_request.write = write;
50  active_request.data = data;
51  active_request.len = len;
52  active_request.bytes_completed = 0;
53  active_request.bytes_issued = 0;
54  active_request.id = makeUniqueRequestID();
55
56  SequencerMsg msg;
57  msg.getPhysicalAddress() = Address(paddr);
58  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
59  msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
60  int offset = paddr & m_data_block_mask;
61  msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
62    len :
63    RubySystem::getBlockSizeBytes() - offset;
64  if (write)
65    msg.getDataBlk().setData(data, offset, msg.getLen());
66  m_mandatory_q_ptr->enqueue(msg);
67  active_request.bytes_issued += msg.getLen();
68
69  return active_request.id;
70}
71
72void DMASequencer::issueNext()
73{
74  assert(m_is_busy == true);
75  active_request.bytes_completed = active_request.bytes_issued;
76  if (active_request.len == active_request.bytes_completed) {
77    m_hit_callback(active_request.id);
78    m_is_busy = false;
79    return;
80  }
81
82  SequencerMsg msg;
83  msg.getPhysicalAddress() = Address(active_request.start_paddr +
84				     active_request.bytes_completed);
85  assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
86  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
87  msg.getType() = (active_request.write ? SequencerRequestType_ST :
88		   SequencerRequestType_LD);
89  msg.getLen() = (active_request.len -
90		  active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
91		  active_request.len - active_request.bytes_completed :
92		  RubySystem::getBlockSizeBytes());
93  if (active_request.write) {
94    msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
95			     0, msg.getLen());
96    msg.getType() = SequencerRequestType_ST;
97  } else {
98    msg.getType() = SequencerRequestType_LD;
99  }
100  m_mandatory_q_ptr->enqueue(msg);
101  active_request.bytes_issued += msg.getLen();
102}
103
104void DMASequencer::dataCallback(const DataBlock & dblk)
105{
106  assert(m_is_busy == true);
107  int len = active_request.bytes_issued - active_request.bytes_completed;
108  int offset = 0;
109  if (active_request.bytes_completed == 0)
110    offset = active_request.start_paddr & m_data_block_mask;
111  assert( active_request.write == false );
112  memcpy(&active_request.data[active_request.bytes_completed],
113	 dblk.getData(offset, len), len);
114  issueNext();
115}
116
117void DMASequencer::ackCallback()
118{
119  issueNext();
120}
121
122void DMASequencer::printConfig(ostream & out)
123{
124
125}
126
127
128DMASequencer *
129DMASequencerParams::create()
130{
131    return new DMASequencer(this);
132}
133