DMASequencer.cc revision 6467:5670eee2a866 
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/SequencerMsg.hh"
8#include "mem/protocol/SequencerRequestType.hh"
9#include "mem/ruby/system/System.hh"
10
11DMASequencer::DMASequencer(const string & name)
12  : RubyPort(name)
13{
14}
15
16void DMASequencer::init(const vector<string> & argv)
17{
18  m_version = -1;
19  m_controller = NULL;
20  for (size_t i=0;i<argv.size();i+=2) {
21    if (argv[i] == "controller")
22      m_controller = RubySystem::getController(argv[i+1]);
23    else if (argv[i] == "version")
24      m_version = atoi(argv[i+1].c_str());
25  }
26  assert(m_controller != NULL);
27  assert(m_version != -1);
28
29  m_mandatory_q_ptr = m_controller->getMandatoryQueue();
30  m_is_busy = false;
31  m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
32}
33
34int64_t DMASequencer::makeRequest(const RubyRequest & request)
35{
36  uint64_t paddr = request.paddr;
37  uint8_t* data = request.data;
38  int len = request.len;
39  bool write = false;
40  switch(request.type) {
41  case RubyRequestType_LD:
42    write = false;
43    break;
44  case RubyRequestType_ST:
45    write = true;
46    break;
47  case RubyRequestType_NULL:
48  case RubyRequestType_IFETCH:
49  case RubyRequestType_Locked_Read:
50  case RubyRequestType_Locked_Write:
51  case RubyRequestType_RMW_Read:
52  case RubyRequestType_RMW_Write:
53  case RubyRequestType_NUM:
54    assert(0);
55  }
56
57  assert(!m_is_busy);  // only support one outstanding DMA request
58  m_is_busy = true;
59
60  active_request.start_paddr = paddr;
61  active_request.write = write;
62  active_request.data = data;
63  active_request.len = len;
64  active_request.bytes_completed = 0;
65  active_request.bytes_issued = 0;
66  active_request.id = makeUniqueRequestID();
67
68  SequencerMsg msg;
69  msg.getPhysicalAddress() = Address(paddr);
70  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
71  msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
72  int offset = paddr & m_data_block_mask;
73  msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
74    len :
75    RubySystem::getBlockSizeBytes() - offset;
76  if (write)
77    msg.getDataBlk().setData(data, offset, msg.getLen());
78  m_mandatory_q_ptr->enqueue(msg);
79  active_request.bytes_issued += msg.getLen();
80
81  return active_request.id;
82}
83
84void DMASequencer::issueNext()
85{
86  assert(m_is_busy == true);
87  active_request.bytes_completed = active_request.bytes_issued;
88  if (active_request.len == active_request.bytes_completed) {
89    m_hit_callback(active_request.id);
90    m_is_busy = false;
91    return;
92  }
93
94  SequencerMsg msg;
95  msg.getPhysicalAddress() = Address(active_request.start_paddr +
96				     active_request.bytes_completed);
97  assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
98  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
99  msg.getType() = (active_request.write ? SequencerRequestType_ST :
100		   SequencerRequestType_LD);
101  msg.getLen() = (active_request.len -
102		  active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
103		  active_request.len - active_request.bytes_completed :
104		  RubySystem::getBlockSizeBytes());
105  if (active_request.write) {
106    msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
107			     0, msg.getLen());
108    msg.getType() = SequencerRequestType_ST;
109  } else {
110    msg.getType() = SequencerRequestType_LD;
111  }
112  m_mandatory_q_ptr->enqueue(msg);
113  active_request.bytes_issued += msg.getLen();
114}
115
116void DMASequencer::dataCallback(const DataBlock & dblk)
117{
118  assert(m_is_busy == true);
119  int len = active_request.bytes_issued - active_request.bytes_completed;
120  int offset = 0;
121  if (active_request.bytes_completed == 0)
122    offset = active_request.start_paddr & m_data_block_mask;
123  assert( active_request.write == false );
124  memcpy(&active_request.data[active_request.bytes_completed],
125	 dblk.getData(offset, len), len);
126  issueNext();
127}
128
129void DMASequencer::ackCallback()
130{
131  issueNext();
132}
133
134void DMASequencer::printConfig(ostream & out)
135{
136
137}
138